Lexicon RV-8 Service Manual page 92

External Registers (U20 and U21)
U20 and U21 are octal D-flops that provide software control for the following:
•
Resets to the DSP engines
•
Resets to the expansion ports
•
Control of external trigger voltages
•
Amplifier Soft Start and Main Relays
•
Status LEDs for debugging and boot monitoring
•
FLASH Write Protect
When the unit is powered up, these D-flops are cleared to zero, placing all DSPs and expansion ports into
a reset state. In addition, the external triggers, amp relays, and status LEDs are held in an inactive state.
The Flash boot sector write protect is active. These flops are strobed by an address decoded signal
provided by the CPLD on sheet seven of the schematic. Refer to the Programmers Guide Revision 6 for
further details regarding address decoding and bit field definition.
The test LED signals are also broken out to a row of test pads represented by J10.
RESET/ Buffer (U45)
U48 provides a buffered equivalent of the RESET/ signal to the FPGA, and to off-board components on
the Front Panel PCB, the Amplifiers, and the Video PCB. All reside within the 5 Volt domain.
Proprietary Algorithm DSP 1 and 2 Host Interface (Sheet 3)
This sheet contains the system clock generator, spread spectrum generator, and the host interface and
configuration blocks of both SHARC engines.
Clock Generator and Buffers (U46 and U47)
U47 is a standard Hex Inverter of which one stage is configured as a Colpitts Oscillator comprised of Y2,
R165, C159, and C160. This circuit generates a 12.500MHz square wave at CMOS levels. R165 provides
hysteresis for the gate, initiating and sustaining a reliable switching characteristic, while C159 and C160
provide the proper AC load to the reactive element of Y2. The second stage of this circuit is another gate
from the hex package that simply buffers the output of the oscillator, presenting a minimal load to it while
providing drive capability. Final buffering to the remainder of the 5V domain of this board is provided by
yet another gate from U47, while buffering to the 3.3V domain is provided by U46.
Spread Spectrum Generator (U48)
U48 is a device that deliberately introduces a certain amount of clock jitter to any clock provided to the
CKI pin (1). The purpose of this is to provide a quick solution to EMI emissions. By introducing a small
amount of jitter to the system, the overall emission level is averaged out over a very wide band of
frequencies, rather than isolated spikes of RF being emitted from a relatively low baseband of noise. The
effect is an instantaneous change in duty cycle of the output clock at any given time. The amount of
modulation is dependent on the state of the SS input pin (4). When this pin is high, the instantaneous duty
cycle of the clock at the CKO pin (5) may have increased or decreased by as much as 3.75%. When the
SS pin is low, the duty cycle variation is limited to 1.25%. The FS2 and FS1 pins (8 and 7) select the
frequency range that the input clock falls within. FB17 provides a cleaner equivalent of the 5V digital
supply rail to the Spread Spectrum device while C161 acts as a standard de-coupling capacitor.
As of this date, the Spread Spectrum operation has not been selected for use in this system. Resistors
R166 and R170 select between straight unmodified system clocking or spread spectrum clocking. The
default operation of this unit is with R166 in place: straight unmodified clocking.
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RV-8 Service Manual