Lexicon RV-8 Service Manual page 106

FPGA Programming Source Configuration Table
R128 R129 R130
IN IN IN
OUT OUT OUT
Host Bus Interface
Signals: CPUADDR[9:0], LVDATA[7:0], CPUCS2/, CPUWRL/, CPURD/, BUFDIR, CPUCLKOUT, RESET/
The AVRX FPGA internal registers are contained entirely within the CS2/ memory space of the host CPU.
Therefore, the memory space that these registers occupy begins at a base address of 0x00800000.
Register accesses are implemented over a byte wide data bus LVDATA[7:0] with 1Kbytes of addressing
implemented over a 10-bit wide address bus CPUADDR[9:0]. Write accesses are made when the host
CPU asserts CPUWRL/ and CPUCS2/ to low states. Read accesses are made when the host CPU
asserts CPURD/ and CPUCS2/ to a low state.
The FPGA has 5 volt tolerant IO, so the address, chip select, read and write control lines come directly
from the CPU. During read cycles, the FPGA places data on the bus at 3.3V logic levels. This must be
level shifted into the 5V domain to be reliably read by the CPU. The bi-directional ports on sheet two of
this schematic provides this level translation to and from the CPU. The direction of these level-shifting
transceivers is controlled by BUFDIR. This signal is low during write cycles to the FPGA, and high during
read cycles from the FPGA.
CPU accesses to and from the FPGA are synchronous with the core frequency of the host processor,
25MHz. This clock is provided by the host to the FPGA as CPUCLKOUT.
RESET/ is a power-up reset signal that clears the state of the internal registers to zero. This signal serves
little more purpose than to be a fail safe mechanism to ensure proper resetting of the FPGA, as this
device is cleared whenever the power to the unit is removed. The FPGA is re-configured at each power-
up and boot phase.
Interrupt Sources
Signals: WCLKDIV8INT/, LVKYBDIRQ/, LVDSPABIRQ/, LVCRYIRQ/, LVVIDTUNIRQ/
WCLKDIV8INT/ is an interrupt to the SHARC DSPs that occurs once every eight audio samples being
presented to the SPORT IO.
LVKYBDIRQ/ is an interrupt to the host CPU that is generated each time a button on the front panel is
pressed. A second interrupt is generated when the key is released. This carries a host interrupt priority of
level 0. This interrupt is level shifted to 5V prior to being presented to the CPU.
LVDSPABIRQ/ is an interrupt to the host CPU that is generated whenever a read or write transaction via
the SHARC SPI ports has been completed. This carries a host interrupt priority of level 2. This signal is
level shifted to 5V prior to being presented to the CPU. At present, this interrupt is masked off and unused
by system software.
6-30
FPGA PROGRAMMING CONFIGURATION
R131 R133 R134
IN OUT OUT
OUT IN IN
R135 R148 R149
OUT IN OUT
IN OUT IN
RV-8 Service Manual
R150 R15 R157 R158
1
IN OUT OUT IN
OUT IN IN OUT
MODE
Host
Programming
(Default)
EPROM
Programming
(Development)