Lexicon RV-8 Service Manual page 102

SPI Interface
Signals: CRY_SCS/, CRY_SPICLK, CRY_RXD, CRY_TXD, CRY_INTREQ/, DSPASPICLK, DSPARXD,
DSPATXD, CRY_FCS/, CRY_FINTREQ/, HINBSY
During the boot phase of RV-8, algorithm code is loaded into the format FLASH and then into the on-
board SRAM. All external memory is accessed through DSPC via its SPI port. As demonstrated with the
SHARC devices, the two SPI ports for DSPAB and DSPC are shared, with each one selected by
independent chip select signals. Host instructions to DSPC are transmitted from the FPGA via CRY_RXD.
Status from DSPC is transmitted back to the FPGA/Host via CRY_TXD. Data on both ports is
synchronous with CRY_SPICLK. All transfers to and from DSPC take place when CRY_SCS/ is asserted
low. DSPC only serves to interface to external memory. The available post-processing of audio data is
not utilized in this application. CRY_INTREQ/ is an open drain output that is asserted low when DSPC
has control data that requires host CPU attention. This signal is pulled up to +2.5V via a section of RP10.
DSPAB implements the following audio algorithms:
•
Dolby Digital EXTM
•
Dolby Pro Logic IITM
•
DTS-ES 96/24TM
•
DTS 96/24TM
•
DTS-ES
•
Discrete 6.1TM
•
DTS-ES Matrix 6.1TM
•
DTS Digital SurroundTM
•
DTS Virtual 5.1TM
•
Surround 6.1 (C.O.S. 6.1)TM
•
THX Surround EXTM
•
THX Ultra2 CinemaTM.
2
The I S audio streams coming in to the Format Processor are interrogated via the DSPAB SPI port and its
P
P
status is reported back to the CPU. The SPI port for DSPAB is selected by asserting CRY_FCS/ low.
CRY_FINTREQ/ is an open drain output that is asserted low when DSPAB has control data that requires
the host CPU attention. This signal is pulled up to +2.5V by a 3.3K resistor.
Provision is made to utilize the SPI signals for SHARC U16, DSPASPICLK, DSPARXD, and DSPATXD.
This provision would be selected by installing R101, R103, and R104 and de-installing R100, R102, and
R105. This provision is not implemented in this application.
HINBSY is an output signal the status of which is latched into a control register within the FPGA. The
CPU polls this register bit. If this bit is high, it indicates that either DSPAB or DSPC has not read data
written via SPI. No other data may be written until this bit is cleared to 0 internally.
All SPI signals are broken out to test points for ease of monitoring.
Unused Pins
Pins: CS/, WR/, RD/, A0, A1, HDATA[7:0], FA0, FA1, FDATA[7:0], CMPREQ, CMPCLK, CMPDAT,
LRCLKN, SCLKN, SDATAN[3:0]
All above listed pins function either as parallel host interface pins or as unused audio channel inputs. As
such they are unused in this application and therefore are pulled up to +2.5V by a section of RP7.
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RV-8 Service Manual