Lexicon RV-8 Service Manual page 95

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incorporation of the bank bits within the address space. The following table illustrates the internal to
external address multiplexing.
SHARC DSP Internal to External Address bit mapping
Row Address
Internal External
A[20:10] A[10:0]
Memory access is contiguous with this scheme. The following diagram illustrates how each 256-word
page is interleaved in relation to the internal address.
Memory Interleave Diagram
0x000000
0x0000FF
0x000100
0x0001FF
0x000200
0x0002FF
0x000300
0x0003FF
0x000400
0x0004FF
0x000500
0x0005FF
0x000600
0x0006FF
0x000700
0x0007FF
0x1FFC00
0x1FFCFF
0x1FFD00
0x1FFDFF
0x1FFE00
0x1FFEFF
0x1FFF00
0x1FFFFF
Bank Bits
Internal
A[9:8]
Bank 0
Bank 1
Bank 2
Bank 3
Bank 0
Bank 1
Bank 2
Bank 3
Bank 0
Bank 1
Bank 2
Bank 3
External Internal
A[14:13] A[7:0]
Column Address
External
A[7:0]
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