Lexicon RV-8 Service Manual page 86

RV-8 Service Manual
The Serial port UARTs are now tested, and if the test passes LED D12 will light, flash if the test fails. The
FPGA (U41) is now programmed. If the operation is successful, LED D13 will light, flash if the operation
fails. If all of these steps are completed successfully, LED D10 will dimly glow. This is due to the LED
being driven with a 4mS square wave. All through these tests, progress may be monitored via a
hyperterminal monitor connected to serial port 0. If a problem exists with this serial connection, LED D11
will light.
Diagnostics continue by testing the Character RAM on the front panel Vacuum-Fluorescent Display.
Connection integrity to the Video Board, Analog I/O Board, AM/FM Tuner Module, and Amplifier SPI ports
is tested as well. The FPGA status is checked by polling it's internal ID register. The Format DSP (U25) is
now taken out of reset and its associated Flash device (U19) is tested. The algorithm DSP devices (U16
and U34) are taken out of reset and loaded with algorithm code. Status is monitored by polling the
internal registers of the DSP devices.
Connection to the amplifiers is tested by serially shifting a single bit up to the amplifiers via the SPI ports,
and then monitoring its return. Power is then briefly applied via the Soft Start Relay, which applies a
current limited full scale voltage to the amp rails. If a problem exists with the amplifier power supply, as
indicated by either the status read back from the SPI ports or by the Brown Out Interrupt, power is
immediately removed and status is indicated on the hyperterminal monitor. If everything checks out, then
the Mains Relay is activated, and the Soft Start Relay is de-activated. The hyperterminal will indicate that
the unit is now ready.
Host Processor (Sheet 1)
This page contains the embedded CPU and its associated DRAM and flash memory for storage of the
boot mode and system control software. In addition, provisions are in place for a separate boot flash
memory and emulator support during software development.
Processor (U33)
The processor is a Hitachi SH7014 single chip RISC. This device implements all system control via a 16-
bit wide data bus over 8Mwords of address space. This address map is split into four chip select areas
(CS[3:0]) of 2Mwords each. The processor is pre-configured by four mode pins MD[3:0] which are hard
coded via zero ohm resistors to a value of 1001 (binary). This establishes that the CS0 memory space
(the memory boot space) is 16-bits wide, and that the on-chip PLL is operating in 4X mode. The
processor runs from a 6.25MHz clock, supplied by a CPLD device (see schematic sheet 7) into the
EXTAL pin (74). With 4X PLL operation, the internal bus of the processor runs at 25MHz. This clock is
sourced to the rest of the system via the PA15_CK pin (83). The PLL is biased and noise filtered by an
external network comprised of R125, R126, C120, and C121.
Serial Ports
Signals: DEBUG_RXD, DEBUG_TXD, USER_RXD, USER_TXD
The CPU provides two asynchronous serial ports which are used as a debug port and as a user port. The
debug port is implemented by PA0_RXD0 (51) and PA1_TXD0 (50). Connecting a hyperterminal to this
port grants the user access to the debugging and register editing tools built into the boot code. During the
boot phase, each step of the process is echoed to the terminal via this debug port as well as any
initialization failures that may occur. The debugger allows the user to manually change register values
within the CPU and each of the peripheral devices attached to the host. It will also allow the running of
configuration scripts to test various functions and features included in the RV-8. Re-programming the
system FLASH is also called into service via the debugger.
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