Lexicon RV-8 Service Manual page 111

Lexicon
Tuner Board Control Interface
Signals: ADA_TUN_CE/, TUN_RDS_CLK, TUN_RDS_DAT
ADA_TUN_CE/ is a chip select that enables SPI transfers to the Tuner Board. The rest of the SPI port is
comprised of ADA_SDATA_IN, ADA_SDATA_OUT, and ADA_LATCH from the Analog Board Control
Interface. Currently the tuner board does not utilize a SPI interface, so the chip select signal is not used.
TUN_RDS_DAT is a bi-directional signal that comprises part of an I
Control register addresses and data are serially shifted up to the tuner board synchronous with the rising
edge of TUN_RDS_CLK.
Analog Board Control Interface
Signals: ADA_SDATA_OUT, ADA_SDATA_IN, ADA_SCLK, ADA_LATCH, ADA_VC_SEL/,
ADA_TUN_CE/, TUN_RDS_CLK, TUN_RDS_DAT
These signals comprise the SPI interface to the Analog Board. Control data to the CODECs is transmitted
from the FPGA via ADA_SDATA_OUT and status information is received via ADA_SDATA_IN. Both
signals are synchronous with serial shift clock ADA_SCLK. Control data is latched into an eight-bit
register on the Analog Board when ADA_LATCH is in a high state; this occurs at the end of every sample
byte transmitted. ADA_VC_SEL/ is a chip select that enables SPI transfers to the volume controller
devices on the Analog Board. ADA_TUN_CE/ is a chip select that enables SPI transfers to the Tuner
Board. Currently, the Tuner Board does not use SPI control, so this signal is unused.
Analog Board Audio Interface
Signals: REC_ADC_FS/, REC_ADC_FS64/, REC_DAC_FS/, REC_DAC_FS64/, MAIN_FS/,
MAIN_FS64/, MAIN_I2S_OUT[4:1], REC_DAC_I2S_OUT, MAIN_I2S_IN[4:1]
MAIN_I2S_IN1 is the serial data stream sourced from the MAIN A/D Converter on the Analog Board to
the AVRX FPGA. This I
P
left/right analog input pair, the phono preamplifier, microphone 1, microphone 2, or tuner.
MAIN_I2S_IN2 is the serial data stream sourced from the C/SUB A/D Converter on the Analog Board to
the AVRX FPGA. This I
P
left/right analog input pair.
MAIN_I2S_IN3 is the serial data stream sourced from the SIDE A/D Converter on the Analog Board to
the AVRX FPGA. This I
P
left/right analog input pair.
MAIN_I2S_IN4 is the serial data stream sourced from the REC A/D Converter on the Analog Board to the
2
AVRX FPGA. This I S stream is the 24-bit left and right channel data encoded from a selected left/right
P
P
analog input pair, the phono preamplifier, microphone 1, microphone 2, or tuner. These analog sources
are level controlled prior to conversion.
Note that in all cases, the analog sources are level controlled prior to conversion.
REC_ADC_FS/ is the Left/Right framing signal for MAIN_I2S_IN4 sourced from the AVRX FPGA to the
REC A/D Converter on the Analog Board.
REC_ADC_FS64/ is the serial clock for the MAIN_I2S_IN4 data streams. This is sourced from the AVRX
FPGA to the REC A/D Converter on the Analog Board.
2
S stream is the 24-bit left and right channel data encoded from a selected
P
2
S stream is the 24-bit left and right channel data encoded from the number-four
P
2
S stream is the 24-bit left and right channel data encoded from the number-five
P
2
C interface to the Tuner Board.
P
P
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