Lexicon RV-8 Service Manual page 107

Lexicon
LVCRYIRQ/ is an interrupt to the host CPU that is generated whenever a read or write transaction via the
Format Decoder SPI ports has been completed. This carries a host interrupt priority of level 3. This signal
is level shifted to 5V prior to being presented to the CPU. At present, this interrupt is masked off and
unused by system software.
LVVIDTUNIRQ/ is an interrupt to the host CPU that generated whenever RDS data from the tuner module
is ready to be read by the CPU. This interrupt is a shared resource with the video board. It carries an
interrupt priority of level 7. This signal is level shifted to 5V prior to being presented to the CPU. At
present, this interrupt is masked off and unused by system software.
Front Panel Interface
Signals: FP_IR_IN1, FP_SDATA_IN, FP_SDATA_OUT, FP_SDATA_CLK, FP_SDATA_LTCH,
FP_ENCA_IN, FP_ENCB_IN
FP_IR_IN1 is a signal from the front panel remote control infra-red detector. The data from this detector is
a serial bit stream that represents commands that change operative modes of the RV8. When a low to
high transition has been detected from the IR receiver, the internal state machine checks to make sure
the incoming signal is a valid command stream by checking the period of the low to high and high to low
transitions. If it is not, then the state machine waits for another low to high transition in the detector
stream.
If the incoming stream is a valid command stream, then the data extracted is compared to a look-up table
of valid code values. This value is then stored in a RAM buffer that is polled by the host CPU.
FP_SDATA_IN is part of a four-wire interface that controls the front panel LED display and pushbutton
matrix. This signal is a return stream of data reporting front panel button status to the host CPU. Changes
in button status are serially transmitted to the AVRX FPGA where current status is XOR'ed with the
previous status of the last scan. A retriggerable timer is armed whenever the XOR gate is activated
indicating a change in any of the buttons. This timer sends a host interrupt after button activity has
stabilized for three milliseconds. This three millisecond period filters any switch bounce.
FP_SDATA_OUT is the transmitting stream from the main board to the front panel that controls the LED
illumination that is part of the user interface. LED data is written to a RAM buffer internal to the FPGA and
is transmitted up to the front panel at a bit rate of 1MHz.
SDATA_CLK is the clock signal that controls the serial shift of data up and back from the front panel.
FP_SDATA_LTCH is a signal that marks the beginning of an eight bit sample being transmitted to the
front panel.
This four-wire interface works in conjunction with an FPGA on the front panel PCB. Refer to the theory of
operation for this board for further details.
FP_ENCA_IN and FP_ENCB_IN comprise a two-wire quadrature signal from the rotary encoder on the
front panel. The direction of rotation of the encoder is determined by the relative position of a rising edge
on FP_ENCB_IN compared to FP_ENCA_IN. When the encoder is rotated clockwise, the rising edge of
FP_ENCB_IN occurs during a high cycle of FP_ENCA_IN. When the encoder is rotated counter-
clockwise, the edge occurs during a low cycle. The AVRX FPGA debounces the signals from the rotary
encoder, and uses the debounced signals to control a four position Gray Code counter. This counter can
be read by software to determine the position of the encoder.
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