Lexicon RV-8 Service Manual page 112

MAIN_I2S_OUT1 is the 24-bit serial data stream sourced from the AVRX FPGA to the LEFT/RIGHT
FRONT D/A Converter on the Analog Board.
MAIN_I2S_OUT2 is the 24-bit serial data stream sourced from the AVRX FPGA to the CENTER/SUB D/A
Converter on the Analog Board.
MAIN_I2S_OUT3 is the 24-bit serial data stream sourced from the AVRX FPGA to the LEFT/RIGHT SIDE
D/A Converter on the Analog Board.
MAIN_I2S_OUT4 is the 24-bit serial data stream sourced from the AVRX FPGA to the LEFT/RIGHT
REAR D/A Converter on the Analog Board.
MAIN_FS/ is the Left/Right framing signal for the MAIN_I2S_IN[3:1] and the MAIN_I2S_OUT[4:1] data
streams sourced from the AVRX FPGA to the MAIN, C/SUB, and SIDE A/D and D/A Converters on the
Analog Board.
MAIN_FS64/ is the serial clock for the MAIN_I2S_IN[3:1] and the MAIN_I2S_OUT[4:1] data streams.
This is sourced from the AVRX FPGA to the MAIN, C/SUB, and SIDE A/D and D/A Converters on the
Analog Board.
REC_DAC_I2S_OUT is the 24-bit data stream sourced from the AVRX FPGA to the Record Zone D/A
converter on the Analog Board.
REC_DAC_FS/ is the Left/Right framing signal for REC_DAC_I2S_OUT. It is sourced from the AVRX to
the Record Zone D/A converter.
REC_DAC_FS64/ is the serial clock for REC_DAC_I2S_OUT.
The Zone 2 left/right VAR and FIX outputs are sourced by the Record Zone D/A converter.
Power Amplifier SPI Control
Signals: CTRL_DATA, STAT_DATA, SER_CLKA, DATA_LATCHA, CTRL_DATB, STAT_DATB,
SER_CLKB, DATA_LATCHB
STAT_DATA is the receive path from the four-channel power amplifier. Data from this signal is stored in a
2x8 bit RAM internal to the AVRX, from which the host may determine the ready status and clip status of
each channel. The following table illustrates the mapping of the internal RAM.
Address Bits
Base + 0 7:0
Base + 1 7:4
Base + 1 3:0
Four Channel Status RAM Table
CTRL_DATA is the transmit path to the four-channel power amplifier. Control data from the Host CPU is
loaded into an internal 2x8 bit RAM that is in turn serially shifted out to the four-channel amplifier board.
The only control data currently being transmitted is in the form of four ready acknowledge bits, each of
which activates a relay that places the speaker terminals into circuit with the amplifier outputs. The table
on the next page illustrates the mapping of the internal RAM.
6-36
Signal
Control bits [7:0] from the previous SPI cycle
Clip Indicator for Channels 4:1 (CLIP[4:1])
Ready monitor for channels 4:1 (RDY_MON[4:1])
RV-8 Service Manual