Lexicon RV-8 Service Manual page 108

RV-8 Service Manual
Digital Audio I/O
Signals: SPDIF_COAX_IN[4:1], SPDIF_OPTO_IN[4:1], DIG_REC_OUT
Provision is made within the RV-8 for eight S/PDIF inputs, four from coaxial sources, and four from optical
fiber sources. The coax sources are signal conditioned and buffered prior to being routed to the AVRX
FPGA. The optical sources require no additional conditioning and so are routed directly to the AVRX from
the TORX connectors. The AVRX determines the word clock from incoming S/PDIF samples via phase
comparison with the system word clock from the on-board PLL circuitry. The PLL is adjusted until the
system word clock is the same as the S/PDIF word clock. The S/PDIF inputs are sampled with a clock
that is 1024 times the sample rate in 96/88.2 KHz mode and 2048 times the sample rate in 48/44.1 kHz
mode to compensate for sources that display a significant amount of jitter. This oversample scheme
eliminates the need for a two stage PLL. The S/PDIF channel status bits from all channels may be read
through the host interface.
DIG_REC_OUT is sourced from the AVRX FPGA. SPORT data from the downmix port of the SHARCs or
digital audio data from the Record Zone DAC is converted to a Bi-phase mark signal with parity added by
the AVRX.
Format Decoder Interface
Signals: CRY_CLKSEL, CRY_TXD, CRY_RXD, CRY_SPICLK, CRY_FCS/, CRY_SCS/, CRY_INTREQ/,
CRY_FINTREQ/, HINBSY, DEC_IN_FSI, DEC_IN_SCKI, DEC_SDI, DEC_MCKI, DEC_OUT_SCKI,
DEC_OUT_FSI, DEC_SDO[3:0]
CRY_CLKSEL is a programmable bit within the MUTE/IR control register that sets the internal operating
speed of the Format Decoder. When this bit is high, the internal logic of the Format Decoder runs at the
input clock rate. When low, the Format Decoder runs at the higher frequency of its internal PLL. The
power up mode of this pin is low.
CRY_TXD transmits control data to the Format Decoder utilizing a modified SPI (Serial to Parallel
Interface) protocol. Control data is written to the internal Format Decoder SPI Control RAM by the system
software and serially shifted out via this pin.
CRY_RXD receives control status information from the Format decoder in serial form. This data is stored
within the Format Decoder SPI Status RAM and is polled by the system software.
CRY_SPICLK is the shift clock used by the SPI protocol to serially shift data into and out of the Format
Decoder. The speed of this clock is controlled by CRY_CLKSEL. This clock must be in slow mode when
programming the Format Decoder FLASH RAM during boot up.
CRY_FCS/ is the chip select for the DSPAB section of the Format Decoder. This chip select is enabled
when bit 0 in the SPI Chip Select Register is set high. This register bit must be set before data is written
to the Format Decoder SPI Control RAM. The DSPAB section of the Format Decoder is responsible for all
algorithm decoding as listed on page 6-27. SPI transfers are initiated when the Format Decoder SPI DMA
Block Size Register is loaded with the number of bytes to be transferred. When a transaction has been
completed, the host processor must reset the chip select bit low.
CRY_SCS/ is the chip select for the DSPC section of the Format Decoder. This chip select is enabled
when bit 1 in the SPI chip select register is set high. This register bit must be set before data is written to
the Format Decoder SPI Control RAM. The DSPC section of the Format Decoder is responsible only for
accessing the FLASH device attached to the Format Decoder. SPI transactions are handled in the same
manner as for CRY_FCS/.
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