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iSBC 80/30
4-25. ADDRESS BUS
The address bus is shown in weighted lines in figures 4-1
and 4-2. The lower eight bits (ADO-AD7) of the memory
address or I/O address (depending on whether a memory ,
reference machine cycle or an I/O reference machine
cycle is in progress) are output by the CPU during the first
clock cycle (T
1).
The CPU ADO-AD7 pins become the
source to or input from the data bus during the second and
third cycles (T
2
and T
3).
The trailing edge of the Address
Latch Enable (ALE) signal issued by the CPU during T
1
strobes these eight address bits into Latch A23 (2ZD3).
The lower eight address bits (ABO-AB7) from A23 are
placed on the iSBC 80/30 address bus together with the
high-order address bits (AB8-AB 15). These address bits
are decoded by the following:
a.
AB2-AB7 to I/O Address Decoder A50 (6ZA 7).
b.
ABA-ABF to PROM Address Decode Logic
(sheet 3).
c.
ABO-ABB to PROM A25/A37 (3ZA3).
d.
ABD-ABF to On-Board RAM Decoder A17 (3ZD7).
4-26. BUS TIME OUT
Bus Time Out one-shot A38 (lZC7) is retriggered by the
leading edge of the ALE signal, which is asserted by the
CPU during T
1
of every machine cycle. If the CPU is
halted, or if the CPU is hung up in a wait state for approxi-
mately 10 milliseconds, A38 times out and asserts the
BTMO signal on pin 34 of the auxiliary bus (P2). If
jumper 115-116 is installed, the BUS TIME OUT/ signal
(A38 pin 6) drives the CPU READY line high through
gates A39 and A28 and allows the CPU to exit the wait
state.
The BUS TIME OUT/ signal is also applied to interrupt
jumper matrix post 122 (7ZC3). If jumpered to the CPU
RST 7.5 input and A38 is retriggered following a CPU
hang-up state, the rising edge of BUS TIME OUT/ will
cause an interrupt to report this event.
4-27. DATA BUS
The CPU ADO-AD7 pins become the source or destina-
tion of the data bus DBO-DB7 during T
2
and T
3
clock
cycles. Data can be sourced to or input from the follow-
ing:
a.
Data Buffer A24 (4ZC6).
b.
Data Buffer A52 (9ZD6).
Principles of Operation
4-28. READ/WRITE SIGNAL GENERATION
The COMMAND/ signal, which is used in conjunction
with the various on-board read/write operations, is gen-
erated by A45-3 (2ZB4) when the CPU RD/ orWR! signal
is true. The following paragraphs describe how the
various I/O and memory control signals are generated.
4-29.
I/O CONTROL SIGNALS. The I/O control sig-
nals (2ZC2) are derived simply by gating the status of the
CPU 10/M, RD/, and
WR!
pins. For example, the I/O
ADR signal is the buffered IO/M pins status; the I/O
WRT/ signal is the logical AND of the 10/M and
WR!
pin
status.
4-30.
MEMORY CONTROL SIGNALS. The MEM
ADR, MEMRD/, and MEMWR! signals (2ZB2, 2ZC2)
are also derived simply by gating the status of the CPU.
10/M, RD/, and
WR!
pins. For example, the MEM ADR
signal is the buffered and inverted IO/M pin status; the
MEMWR! signal is the logical AND of the
WR!
and
inverted IO/M pin status.
TheADV MEM RD/ and ADV MEM WRT/ are derived
by multiplexing the CPU SO and S 1 pin status. Refer to
table 4-1. During all memory references, the CPU 10/M
status pin is low and activates the gate input to 8:4 Multi-
plexer A35. The select pin of A35 is controlled by the SO
pin status; when SO
=
0, the" A" inputs are selected and,
when SO
=
1, the "B" inputs are selected.
For a memory read operation, SO
=
0 and S 1
=
1 and a
logic 1 appears on A35 pin 12. The trailing edge of the
CPU ALE signal clocks Quad "D" Flip-Flop A34 and
A34 pin 14 asserts the AD V MEM RD/ signal.
For a memory write operation, SO
=
1 and SI
=
0 and a
logic 1 appears on A35 pin 7. The trailing edge of ALE
clocks A34 and A34 pin 11 asserts the ADV MEM WRT/
signal.
For a memory fetch operation, SO
=
1 and SI
=
1 and,
since the S 1 status is applied to both the 4 A and 4 B inputs,
the ADV MEM RD/ signal is generated as described
above for the memory read operation.
When the read, write, or fetch operation is complete, the
CPU RD/ or
WR!
pin goes false and Flip-Flop A44
(2ZB3) is clocked and set. The output at A44-6 clears
A?4; the next rising edge of ALE clears A44.
4-31. DUAL PORT CONTROL LOGIC
The Dual Port Control logic (figure 5-2 sheet 9) allows the
on-board RAM facilities to be shared by the on-board
, CPU and another bus master via the Multibus. When not
4-9
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