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Principles of Operation
ROM/EPROM chip select decoders. When address bits
ABA-ABF are true for the address ranges specified
above, PROM AACK! signal is true; when the MEMRD/
signal is also asserted during a read operation, the PROM
ENABLE/ and PROM AACK! signals are true. PROM
ENABLE/ turns on Data Buffer A24 (4ZC6), whose
transmit function is enabled by CPU S 1
=
1, and PROM
AACK! drives the CPU READY line high via A28-6
(1DZS). The decoded output of A49-8 selects the ROM/
EPROM chip in A2S; the decoded output of A49-6 selects
the ROM/EPROM chip in A37. When the chip is enabled,
the contents of the location specified by ABO-ABB are
transferred to the CPU via Data Buffer A24.
4-39. RAM OPERATION
As described in paragraph 4-31, the Dual Port Control
logic allows the on-board RAM facilities to be shared by
the on-board CPU and by another bus master via the
Multibus. The following paragraphs describe briefly the
RAM Controller and the overall operation of how the
RAM is addressed for read/write operation.
4-40. RAM CONTROLLER. All address and control
inputs to the on-board RAM is supplied by RAM Control-
ler A66 (3ZDS). The RAM Controller provides a 64 -cycle
RAS/CAS refresh timing cycle to dynamic RAM chips
A 77 -A84. Default jumper 110-111 holds the REFRESH
RQT signal false and the RAM Controller operates in the
automatic refresh mode. In the automatic refresh m.ode, a
read or write request can be delayed if a refresh cycle is in
progress. Option jumper position 110-106 allows the
REFRESH RQT signal to be controlled by the CPU
READY line and thereby implement the invisible refresh
mode. In the invisible refresh mode, the RAM Controller
works around memory accesses by refreshing RAM dur-
ing the CPU instruction decode clock cycle which follows
each instruction fetch. Refresh occurs during T
4
but, if the
access is greater than the refresh time, the RAM Control-
ler will automatically refresh RAM. Thus, the RAM will
not generate CPU wait states but it will consume more
power.
The RAM Controller, when enabled with a low input to its
PCS/ pin, multiplexes the address to the RAM chips.
Low -order address bits AO-A6 are presented at the RAM
input pins and RAS/ is driven low at the beginning of the
first 8202 clock cycle after RAM RD/ or RAM WRT/ is
active. High-order address bits A7-A13 are presented at
the RAM input pins and CASt is driven low during the
second clock cycle after the RAS/ address hold time is
satisfied.
The RAM Controller then examines its RD/ and WRT/
inputs. If RD/ is low, the RAM Controller drives its WE/
output high to provide a Read signal to RAM; ifWRT/ is
low, the RAM Controller drives its WE/ output high to
provide a write signal to RAM. If RAM RD/ is asserted,
4-14
iSBC 80/30
Memory Data Buffer A76 is enabled and RAM data is
latched into A 76 when RAM XACK/ is subsequently
driven low.
When the memory cycle begins, the RAM Controller
drives its SACK/ output low; SACK! is used as the RAM
AACK! signal. When the cycle is complete (i.e., data is
valid), drives its XACK/ output low. The SACK/ and
XACK/ outputs go high when the RD/ or WRT/ input goes
high.
4-41. ON
BOARD
READ/WRITE
OPERA-
TION. When MEM ADR goes true, Address Decoder
A17 (3ZD7) decodes address bits ABD-ABF. The de-
coded output from A17 goes low and (1) asserts ON BD
RAM RQT/ to the Dual Port Control logic and (2) drives
the RAM Controller PCS/ input low. The RAM Control-
ler then multiplexers the address to RAM and, depending
on which input command (RAMRD/ or RAMWRT/) is
true, drives the WE/ output pin high or low. (The WE/ pin
is driven high for a read and driven low during a write.)
The SACK/ signal, which is asserted at the beginning of
the memory cycle, generates the RAM AACK! signal.
When RAM AACK/ goes true, the Dual Port Control
logic generates the RAM QAACK! signal, which is qual-
ified by being in the master mode. The XACK/ signal,
which is asserted when the data is valid, generates the
RAM XACK! signal.
When RAM QAACK/ goes true, the READY input is
driven high to the CPU to prevent a wait state. By the time
the CPU timing has progressed to T3 of the memory
cycle, the RAM Controller has already asserted XACK!
and the data is valid; i.e., the data has been written into
RAM from the data bus or has been read from RAM onto
the data bus. The XACK! signal, however, is not used by
the CPU during on-board RAM access.
4-42. BUS READ/WRITE OPERATION. When
another bus master has control of the multibus, that bus
master can address the iSBC 80/30 as a slave RAM
device. Assuming that the bus master has a 20-bit address-
ing capability, ADRO/-ADRF/ and ADRIO/-ADR13/ are
placed on the Multibus and then either MWTC/ or
MRDC/ is asserted. Address bits ADRIO/-ADRI3/ are
decoded by A69 (SZC6) and ADRD/ -ADRF/ are decoded
by A68 (SZBS). (A description of 16-bit and 20-bit ad-
dress assignment for bus access of RAM is given in'
paragraphs 2-17 through 2-19.) The decoded output of
A69 provides an enable input to A68. The decoded output
of A68 drives the SLAVE RAM RQT/ signal low to the
Dual Port Control logic.
Assuming no CPU access of RAM is in progress, the
SLAVE MODE/ signal is driven low and address bits
ADRO/-ADRF/ are transferred through Address Buffers
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