On-Board 8085A Access; System Access - Intel iSBC 80 Hardware Reference Manual

iSBC 80/30
Preparation for Use
Table 2-4. Jumper Selectable Options
Function
Fig. 5-1 Fig. 5-2
Description
Grid Ref. Grid Ref.
ROM/EPROM Six jumpers accommodate one of four types of user-installed ROM or
Configuration EPROM chips. One jumper required between two posts in each of
the following six groups of posts:
ZC3 3ZB7
112 thru 114)
ZC3 3ZC6 157 thru 159
Default jumpers accommodate Intel 2716 EPROM
ZC3
3ZB4
153 thru 156
ZD2 3ZA3 84 thru 88
or 2316E ROM chips. Refer to paragraph 2-14 if
ZD2 3ZA4 99 thru 101
reconfiguration is required.
ZD2 3ZA3 102 thru 105
On-Board RAM
ZD2 3ZD7,3ZD6
One jumper wire selects 8K or 16K access and one jumper wire selects
(On-Board Access) base address for on-board 8085A access of on-board RAM. JumperW1
default position *A-B selects 16K access and default jumper *98-92
selects base address 4000H. Refer to paragraphs 2-15 and 2-16 if
reconfiguration is required.
On- Board RA M
16-Bit Address System: Three jumper wires select base address for
(System Access)
system access:
ZB7
5ZC6 W5 (one): Must be set to position *K-L.
ZB7 5ZB6
W4 (one): 8K or 16K access.
ZB7 5ZB5
171 thru 180 (one): Base address.
Refer to paragraphs 2-17 and 2-18.
20-Bit Address System: Five jumper wires select base address for
system access:
ZB7 5ZC7 W6 (two): Upper or lower 512K space.
ZB7
5ZC6 W5 (one): 65K page select.
ZB7
5ZB6 W4 (one): 8K or 16K access.
ZB7
5ZB5 171 thru 180 (one): Base address.
Refer to paragraphs 2-17 and 2-19.
Bus Clock
ZB7 5ZA4 Default jumper *165-166 routes Bus Clock signal BCLKI to the Multibus.
(Refer to table 2-13.) Remove this jumper only if another bus master
supplies this signal.
Constant Clock
ZB7
5ZA4
Default jumper *167-168 routes Constant Clock signal CCLK/ to the
Multibus. (Refer to table 2-13.) Remove this jumper only if another bus
master supplies this signal.
Bus Priority Out ZB7 8ZD2
Default jum per * 169-170 routes Bus Priority Out signal BPRO/ to the
Multibus (Refer to table 2-13.) Remove this jumper only in those
systems employing a parallel priority bus resolution scheme. (Refer
to paragraph 2-27.)
Bus Priority
One jumper defines one of two modes of resolving bus contention in a
Resolution
multiple bus master system:
ZB7
8ZD6
*162-163: Can request Multibus as needed.
163-164: Always requesting Multibus; .should only be used when
iSBC 80/30 has lowest priority.
Auxiliary Backup ZB5
1ZC5,1ZB5 If auxiliary backup batteries are employed to sustain memory during ac
Batteries
power outages, remove default jumpers *W8, *W9, and *W10.
On-Board -5V
ZB6 1ZB2
The 80/30 requires a -5V supply for Intel 2708 EPROM chips and a
Regulator
-5V AUX input for the on-board RAM chips. The system -5V supply
is mandatory only if Intel 2708 EPROM chips are employed. If
Intel 2708 EPROM chips are not employed and no system -5V
supply is available, the -5 AUX input to the on-board RAM chips can
be supplied by the on-board -5V regulator or by an auxiliary backup
battery. (The on-board -5V regulator operates from the system
-12V supply.) If neither a system -5V supply nor an auxiliary backup
battery is used, enable the -5V regulator by connecting jumper*W10.
2-5