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Programming Information
iSBC 80/30
Table 3-25. Typical UPI Data Byte Read Subroutine
;IN41 READS DATA BYTE FROM UPI.
, ;USES-NOTHING; DESTROYS-A.
IN41:
IN
OE5H
ANI
1
JZ
IN41
IN
OE4H
REf
END
;INPUT STATUS
;CHECK OBF FLAG
;WAIT IF EMPTY
Table 3-26. Typical UPI Data Byte Write Subroutine
;OUT 41 WRITES DATA BYTE TO UPI.
:USES-NOTHING; DESTROYS-A.
OUT41:
IN
ANI
JZ
OUT
REf.
END
OE5H
2
OUT41
OE4H
b.
Bit I: Input Buffer Full. The IBF flag is set when the
CPU writes a character to the data bus buffer register
and cleared when the UPI inputs the -contents-6fthe
data bus buffer register to its accumulator.
c.
Bit 2: FO. This general purpose flag, which can be
cleared or toggled under UPI software control, is
used to transfer UPI status information to the CPU.
d.
Bit 3: FI (Control/Data). This flag is set to thecon-
dition of the AO input line when the CPU writes a
character to the data bus buffer register. This flag
can be cleared or toggled under UPI software control.
Tables 3-25 and 3-26, respectively, provides typical
routines for inputting and outputting a data byte from and
to the UPI.
3-47. INTERRUPT HANDLING
The iSBC 80/30 includes fige interrupt inputs: TRAP,
RST 7.5, RST 6.5, RST 5.5, and INTR. The three "re-
start" interrupts (7.5, 6.5, and 5.5) are maskable; the
TRAP is also a "restart" interrupt but is nonmaskable.
The RST 7.5, RST 6.5, and RST 5.5 interrupts cause the
internal execution of an RST instruction if the· interrupts
are enabled and if the interrupt mask is not set by a
previously executed SIM instruction. The nonmaskable
TRAP interrupt causes the execution of an RST instruc-
3-22
;INPUT STATUS
;CHECK IBF FLAG
;WAIT IF NOT READY
tion independent of the state of the interrupt enable or
interrupt mask. The priority and vector location of each of
the restart interrupts are given in table 3-27.
Table 3-27. 8085A CPU Restart Interrupt Vectors
Interrupt
Vector
Priority
Location
TRAP
24
Highest
RST 7.5
3C
2nd
RST 6.5
34
3rd
RST 5.5
2C
4th
3-48. TRAP INPUT
There are special considerations that must be understood
when the TRAP
inte~pt
is used. The fact that the TRAP
interrupt is nonmaskable can present problems in at least
two areas.
Interrupt driven systems often contain parameters that
must be modified only within critical regions. A critical
region can be roughly defined as a section of code that
once begun must complete execution before it or another
critical regin that corresponds to the same system parame-
ter(s) can be executed. A TRAP interrupt handler cannot
safely alter such parameters either directly or indirectly by
causing the execution of procedures or tasks that may alter
such parameters.
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