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Principles of Operation
4-32. BUS ACCESS
TIMING.
Figure 4-9 illustrates
Dual Port Control timing for RAM access via the Mul-
tibus. (P-periods PO through PI7 are used only for de-
scriptive references.) When SLAVE RAM RQT/ and
SLA VE RAM RD/ or SLAVE RAM WRT/ are true,
A43 -15 goes high and A43 -6 goes low on the next rising
edge of the clock at the end of PO. (The purpose of A43 -15
is to synchronize the asynchronous command and the
purpose of A43 -6 is to prevent a subsequent CPU request
from aborting a bus access after A55-9 goes high at the
end of PI).
At the end of PI, A55-9 goes high and A55-8 goes low;
A55-8 asserts the SLAVE MODE signal. The outputs of
A55-8 and A43-6 are ANDed to hold A55-9 in the preset
(high) state. At the end of P2, A43-11 goes low and
asserts the OFF BD CS/ signal, which drives the PCS/
input low to RAM Controller A66. The output of A43 -II
also enables pin I of A60-7, A60-3, A60-5, and A60-9,
to gate the RAM RD/ or RAM WRT/ signal to A66.
Approximately one-half to two clock cycles later, A66
asserts the RAM AACK/ signal and, at the end of P3,
A43-15 goes low.
The RAM Controller asserts RAM XACK/ during P13
and SLA VE XACK/ in driven onto the Multibus. The bus
master then first raises the SLAVE RAM RD/ or SLA VE
RAM WRT/ signal and then the SLAVE RAM RQT/
signal. When SLAVE RAM RD/ or WRT/ goes false, the
RAM Controller raises RAM AACK/ and RAM XACK/.
At the end of P15, A43-6 is clocked high. At the end of
P16, A55-9 goes low and A59-8 goes high. At the end of
P17, A43-11 goes high and terminates the OFF BD CS/
signal.
The foregoing discussion pertains only to the operation of
the Dual Port Control for bus access of on-board RAM.
The actual addressing and the transfer of data are dis-
cussed in paragraph 4-42.
4-33. CPU ACCESS
TIMING.
Figure 4-10 illustrates
the Dual Port Control timing for RAM access by the
on-board CPU. (P-periods PO through P13 are used only
for descriptive purposes.) To demonstrate that the CPU
has priority in the access of on-board RAM, figure 4-10
shows that the SLAVE RAM RQT/ and a SLAVE RAM
RD/ or SLAVE RAM WRT/ are active when the CPU
access is. initiated. The timing has progressed through PO
during which time A43-15 has been clocked high and
A43 -6 has been clocked low.
When the ON BD RAM RQT and ADV MEM RD/ are
asserted, the AD V MEM RD/ signal is driven through
A60-15 to assert the RAM RD/ signal. The RAM Control-
ler then asserts RAM AACK/, which is driven through
A62-8 to produce RAM QAACK/. At the end of PI,
A43-15 is clocked low to effectively abort the slave ac-
cess timing cycle. (For a write cycle, the MEM
WR!
signal is used instead of ADV MEM WRT/.
4-12
iSBC 80/30
During PI2 the RAM controller asserts RAM XACK/ (not
used by the CPU) and, during P13, the ADV MEM RD/
and ON BD RAM go false to complete the CPU access.
On the following rising edge of the clock, the SLAVE
RAM RQT/ and SLAVE RAM RD/ or SLAVE RAM
WRT/ signals, which have been held off during the CPU
access, set A43-15 once again to initiate the slave access
timing cycle.
The foregoing discussion pertains only to the operation of
the Dual Port Control for CPU access of on-board RAM.
The actual addressing and the transfer of data are dis-
cussed in paragraph 4-41.
4-34. MULTIBUS INTERFACE
The Multibus interface consists of Bus Controller A67
(8ZD5), bidirectional -Address B us Driver A 72/ A 73
(8ZA2), bidirectional Data Bus Driver A74/A75 (8ZB2),
and the Slave RAM Address Decode Logic (figure 5-2
sheets 3 and 5).
The Bus Controller allows the iSBC 80/30 to assume the
role of a bus master and includes bus arbitration, timing,
and read/write command logic. The falling edge of
BCLK/ provides the timing reference, and bus arbitration
begins when the Qualified Command (QCMD/) signal is
asserted and the address decoders have determined that
the associated Read or Write Command is-not intended for
on-board
VO
or memory. The QCMD/ signal (lZD8),
which is used only for Multibus requests, is derived di-
rectly from the CPU Read (RD/) signal or derived by
delaying the CPU Write (WT/) signal half a clock cycle.
(Delaying WT/ ensures the adequate setup of the address
and data to the Bus Drivers before the Write Command
(IORC/ or MWTC/) is asserted.
The QCMD/ signal activates the Transfer Start Request
(XSTR) input to the Bus Controller, which drives BREQ/
low and BPRO/ high. The BREQ/ output from each bus
master in the system is used by the Multibus when the bus
priority is resolved by a parallel priority scheme as de-
scribed in paragraph 2-27. The BPRO/ output is used by
the Multibus when the bus priority is resolved by a serial
priority scheme as described in paragraph 2-26.
The iSBC 80/30 gains control of the Multibus when the
BPRN/ input to the Bus Controller is driven low. On the
next falling edge of BCLK), the B us Controller drives
BUSY/ and ADEN/ low. The BUSY/ output indicates that
the bus is in use and that the current bus master in control
will not relinquish control until it raises its BUSY/ signal.
The ADEN/ output, which can be thought of as a "master
bus control" signal, enables Address Bus Driver
A72/A73 and Data Bus Driver A74/A75. Since the board
is not in the slave mode, the QSLA VE RQT/ signal is
false (high) and the Address Bus Driver transmit function
is selected. The steering logic composed of A39-6,
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