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Intel 815EG manual available for free PDF download: Design Manual
Intel 815EG Design Manual (196 pages)
Chipset Platform For Use with Universal Socket 370
Brand:
Intel
| Category:
Motherboard
| Size: 1.91 MB
Table of Contents
Table of Contents
3
Introduction
13
Design Guide and Chipset Basic Information
13
Terminology
14
Reference Documents
16
System Overview
17
System Features
18
Figure 1. System Block Diagram
18
Component Features
19
Intel 82815EG GMCH Features
19
Figure 2. Component Block Diagram
19
Intel ® 815 to 815G/EG Signal Name Changes
20
Table 1. Intel 82815 to Intel 82815G Pin Name Changes
20
Intel ® 82801BA I/O Controller Hub 2 (ICH2)
21
Firmware Hub (FWH)
21
Platform Initiatives
21
Universal Motherboard Design
21
Intel ® PC 133
22
Accelerated Hub Architecture Interface
22
Internet Streaming SIMD Extensions
22
Integrated LAN Controller
22
Ultra ATA/100 Support
22
Expanded USB Support
22
Manageability and Other Enhancements
23
AC '97 6-Channel Support
23
Figure 3. AC '97 Audio and Modem Connections
25
Low-Pin-Count (LPC) Interface
26
General Design Considerations
27
Nominal Board Stack-Up
27
Figure 4. Board Construction Example for 60 Ω Nominal Stack-Up
27
Future Designs Require Pull-Ups and Pull-Downs on any Unused Input and I/O Pins
28
Support for P-MOS Kicker "ON": SMAA[9] Is Strapped High by an Internal 50 Kω Pull-Up Resistor
28
Electrostatic Discharge Platform Recommendations
28
Figure 5. Top Signal Layer before the Ground Fill Near the I/O Layer
29
Figure 6. Top Signal Layer after the Ground Fill Near the I/O Layer
29
Figure 7. Bottom Signal Layer before the Ground Fill Near the I/O Area
30
Figure 8. Bottom Signal Layer after the Ground Fill Near the I/O
30
Figure 9. GMCH 544-Ball Μbga* CSP Quadrant Layout (Top View)
31
Component Layouts
31
Figure 10. ICH2 360-Ball EBGA Quadrant Layout (Top View)
32
Figure 11. Firmware Hub (FWH) Packages
33
Universal Socket 370 Design
35
Universal Socket 370 Definitions
35
Table 2. Processor Considerations for Universal Socket 370 Design
35
Table 3. GMCH Considerations for Universal Socket 370 Design
36
Table 4. Intel ® ICH2 Considerations for Universal Socket 370 Design
36
Processor Design Requirements
37
Use of Universal Socket 370 Design with Incompatible GMCH
37
Figure 12. Future 0.13 Micron Socket 370 Processor Safeguard for Universal Socket 370
37
Table 5. Clock Synthesizer Considerations for Universal Socket 370 Design
37
Identifying the Processor at the Socket
38
Figure 13. Processor Detect Mechanism at Socket/Tual5 Generation Circuit
38
Setting the Appropriate Processor VTT Level
39
Figure 14. VTT Selection Switch
39
VTT Processor Pin AG1
40
Figure 15. Switching Pin AG1
40
Identifying the Processor at the GMCH
41
Figure 16. Processor Identification Strap on GMCH
41
Table 6. Determining the Installed Processor Via Hardware Mechanisms
41
Configuring Non-VTT Processor Pins
42
Figure 17. VTTPWRGD Configuration Circuit
42
VCMOS Reference
43
Figure 18. GTL_REF/VCMOS_REF Voltage Divider Network
43
Processor Signal PWRGOOD
44
Figure 19. Resistor Divider Network for Processor PWRGOOD
44
APIC Clock Voltage Switching Requirements
45
Figure 20 Voltage Switch for Processor APIC Clock
45
GTLREF Topology and Layout
46
Figure 21. GTLREF Circuit Topology
46
Power Sequencing on Wake Events
47
Gating of Intel ® CK-815 to VTTPWRGD
47
Figure 22. Gating Power to Intel ® CK-815
47
Figure 23 PWROK Gating Circuit for Intel ® ICH2
48
Ich2
48
System Bus Design Guidelines
49
System Bus Routing Guidelines
49
Initial Timing Analysis
49
Table 7. Intel Pentium
50
Calculations
50
Flt_Min
51
General Topology and Layout Guidelines
52
Figure 24. Topology for 370-Pin Socket Designs with Single-Ended Termination (SET)
52
Table 10. Trace Guidelines for Figure 24
52
Table 11. Trace Width: Space Guidelines
52
Motherboard Layout Rules for AGTL/AGTL+ Signals
53
Ground Reference
53
Reference Plane Splits
53
Processor Connector Breakout
53
Figure 25. AGTL/AGTL+ Trace Routing
53
Minimizing Crosstalk
54
Motherboard Layout Rules for Non-AGTL/AGTL+ (CMOS) Signals
55
Table 12. Routing Guidelines for Non-AGTL/AGTL+ Signals
55
Additional Routing and Placement Considerations
56
Figure 26. Routing for THRMDP and THRMDN
56
THRMDP and THRMDN
56
Electrical Differences for Universal PGA370 Designs
57
THERMTRIP Circuit
57
Figure 27. Example Implementation of THERMTRIP Circuit
57
THERMTRIP Support for 0.13 Micron Technology Processors, A-1 Stepping
58
THERMTRIP Timing
58
PGA370 Socket Definition Details
59
Figure 28 Thermtrip Support for A-1 Stepping 0.13 Micron Technology Processors
59
Table 13. Processor Pin Definition Comparison
59
BSEL[1:0] Implementation Differences
62
CLKREF Circuit Implementation
63
Figure 29. BSEL[1:0] Circuit Implementation for PGA370 Designs
63
Undershoot/Overshoot Requirements
64
Figure 30. Examples for CLKREF Divider Circuit
64
Table 14. Resistor Values for CLKREF Divider (3.3 V Source)
64
Processor Reset Requirements
65
Figure 31. RESET#/RESET2# Routing Guidelines
65
Table 15. RESET#/RESET2# Routing Guidelines (See Figure 31)
65
Processor PLL Filter Recommendations
66
Topology
66
Filter Specification
66
Figure 32. Filter Specification
67
Recommendation for Intel ® Platforms
68
Table 16. Component Recommendations - Inductor
68
Table 17. Component Recommendations - Capacitor
68
Table 18. Component Recommendation - Resistor
68
Figure 33. Example PLL Filter Using a Discrete Resistor
69
Figure 34. Example PLL Filter Using a Buried Resistor
69
Custom Solutions
70
Voltage Regulation Guidelines
70
Decoupling Guidelines for Universal PGA370 Designs
70
VCC CORE Decoupling Design
70
Figure 35. Core Reference Model
70
VTT Decoupling Design
71
VREF Decoupling Design
71
Figure 36. Capacitor Placement on the Motherboard
71
Thermal Considerations
72
Heatsink Volumetric Keep-Out Regions
72
Figure 37. Heatsink Volumetric Keep-Out Regions
73
Figure 38 Motherboard Component Keep-Out Regions
73
Fan Heatsink Keep-Out Adherence for Future Boxed Intel Celeron Processors
74
Figure 39. Keep-Out Requirements for the 370-Pin (Top View)
74
Debug Port Changes
75
Figure 40. TAP Connector Comparison
75
System Memory Design Guidelines
77
System Memory Routing Guidelines
77
Figure 41. System Memory Routing Guidelines
77
System Memory 2-DIMM Design Guidelines
78
System Memory 2-DIMM Connectivity
78
Figure 42. System Memory Connectivity (2 DIMM)
78
System Memory 2-DIMM Layout Guidelines
79
Figure 43. System Memory 2-DIMM Routing Topologies
79
Table 19. System Memory 2-DIMM Solution Space
79
Figure 44. System Memory Routing Example
80
System Memory 3-DIMM Design Guidelines
81
System Memory 3-DIMM Connectivity
81
Figure 45. System Memory Connectivity (3 DIMM)
81
System Memory 3-DIMM Layout Guidelines
82
Figure 46. System Memory 3-DIMM Routing Topologies
82
Table 20. System Memory 3-DIMM Solution Space
82
System Memory Decoupling Guidelines
83
Figure 47. Intel 815 Chipset Platform Decoupling Example
83
Figure 48. Intel ® 815 Chipset Decoupling Example
84
Compensation
85
Display Cache Design Guidelines
87
Display Cache Interface
87
GPA Card Considerations
87
GPA Mechanical Considerations
87
Display Cache Clocking
88
VDDQ Generation
88
Figure 49. Display Cache Input Clocking
88
Integrated Graphics Display Output
89
Analog RGB/CRT
89
Ramdac/Display Interface
89
Figure 50. Schematic of RAMDAC Video Interface
90
Reference Resistor (Rset) Calculation
91
RAMDAC Board Design Guidelines
91
Figure 51. Cross-Sectional View of a Four-Layer Board
91
Figure 52. Recommended RAMDAC Component Placement and Routing
92
RAMDAC Layout Recommendations
93
HSYNC/VSYNC Output Guidelines
93
Figure 53. Recommended RAMDAC Reference Resistor Placement and Connections
93
Intel ® Digital Video out
94
Intel ® DVO Interface Routing Guidelines
94
Intel ® DVO I 2 C Interface Considerations
94
Leaving the Intel DVO Port Unconnected
94
Figure 54. Hub Interface Signal Routing Example
97
Data Signals
98
HREF Generation/Distribution
98
Strobe Signals
98
Compensation
99
Figure 55. Single Hub Interface Reference Divider Circuit
99
Figure 56. Locally Generated Hub Interface Reference Dividers
99
Hub Interface
97
I/O Controller Hub 2 (Intel ICH2)
101
Decoupling
101
Table 21. Decoupling Capacitor Recommendation
101
Power Sequencing on Wake Events
102
Figure 57. Intel ® ICH2 Decoupling Capacitor Layout
102
Power Supply PS_ON Considerations
103
O Subsystem
105
IDE Interface
105
Cabling
105
Cable Detection for Ultra ATA/66 and Ultra ATA/100
105
Combination Host-Side/Device-Side Cable Detection
106
Figure 58. Combination Host-Side / Device-Side IDE Cable Detection
106
Device-Side Cable Detection
107
Figure 59. Device-Side IDE Cable Detection
107
Primary IDE Connector Requirements
108
Figure 60. Connection Requirements for Primary IDE Connector
108
Secondary IDE Connector Requirements
109
Figure 61. Connection Requirements for Secondary IDE Connector
109
Figure 62. Intel ® ICH2 AC '97- Codec Connection
110
Communications Network Riser (CNR)
111
Figure 63. CNR Interface
111
AC '97 Audio Codec Detect Circuit and Configuration Options
112
Figure 64. CDC_DN_ENAB# Support Circuitry for a Single Codec on Motherboard
112
Figure 65. CDC_DN_ENAB# Support Circuitry for Multi-Channel Audio Upgrade
113
Figure 66. CDC_DN_ENAB# Support Circuitry for Two-Codecs on Motherboard / One-Codec on CNR
114
Figure 67. CDC_DN_ENAB# Support for Two-Codecs on Motherboard
114
Valid Codec Configurations
115
SPKR Pin Considerations
115
Table 22. Signal Descriptions
115
Table 23. Codec Configurations
115
AC '97 Routing
116
Figure 68. Example Speaker Circuit
116
Motherboard Implementation
117
Usb
118
Using Native USB Interface
118
Disabling the Native USB Interface of ICH2
119
I/O APIC Design Recommendation
119
Figure 69. USB Data Signals
119
Figure 70. Example PIRQ Routing
120
PIRQ Routing Example
120
Table 24. IOAPIC Interrupt Inputs 16 Thru 23 Usage
120
Smbus/Smlink Interface
121
Figure 71. Smbus/Smlink Interface
121
Smbus Architecture and Design Considerations
122
General Design Issues and Notes
122
Table 25. Pull-Up Requirements for Smbus and Smlink
122
Figure 72. Unified Vcc_Suspend Architecture
123
Figure 73. Unified VCC
123
Pci
125
Figure 75. PCI Bus Layout Example
125
Rtc
126
RTC Crystal
126
Figure 76. External Circuitry for the ICH2 RTC
126
External Capacitors
127
RTC Layout Considerations
127
RTC External Battery Connection
127
Figure 77. Diode Circuit to Connect RTC External Battery
128
RTC External RTCRST Circuit
129
Power-Well Isolation Control Requirements
129
Figure 78. RTCRST External Circuit for ICH2 RTC
129
RTC Routing Guidelines
130
Figure 79. RTC Power Well Isolation Control
130
VBIAS DC Voltage and Noise Measurements
131
LAN Layout Guidelines
131
Table 26. LAN Connect
131
Intel ® ICH2 - LAN Interconnect Guidelines
132
Figure 80. Intel ICH2 / LAN Connect Section
132
Bus Topologies
133
Figure 81. Single-Solution Interconnect
133
Point-To-Point Interconnect
133
Table 27. Single-Solution Interconnect Length Requirements (See Figure 81)
133
Figure 82. LOM/CNR Interconnect
134
LOM/CNR Interconnect
134
Table 28. LOM/CNR Length Requirements (See Figure 82)
134
Crosstalk Consideration
135
Figure 83. LAN_CLK Routing Example
135
Impedances
135
Signal Routing and Layout
135
Line Termination
136
General LAN Routing Guidelines and Considerations
136
General Trace Routing Considerations
136
Figure 84. Trace Routing
137
Power and Ground Connections
138
Figure 85. Ground Plane Separation
138
A 4-Layer Board Design
139
Common Physical Layout Issues
139
Intel ® 82562EH Home/Pna* Guidelines
141
Power and Ground Connections
141
Guidelines for Intel 82562EH Component Placement
141
Crystals and Oscillators
142
Phoneline HPNA Termination
142
Figure 86. Intel ® 82562EH Termination
142
Critical Dimensions
143
Figure 87. Critical Dimensions for Component Placement
143
Table 29. Critical Dimensions for Component Placement (Refer to Figure 87)
143
Intel 82562ET / Intel 82562EM Guidelines
144
Guidelines for Intel 82562ET / Intel 82562EM Component Placement
144
Crystals and Oscillators
145
Intel ® 82562ET / Intel ® 82562EM Termination Resistors
145
Critical Dimensions
145
Figure 88. Intel ® 82562Et/Intel ® 82562EM Termination
145
Figure 89. Critical Dimensions for Component Placement
146
Table 30. Critical Dimensions for Component Placement (See Figure 89)
146
Reducing Circuit Inductance
147
Figure 90. Termination Plane
148
Figure 91. Intel 82562ET/82562EM Disable Circuit
148
Intel ® 82562ET/82562EM Disable Guidelines
148
Figure 92. Dual-Footprint LAN Connect Interface
149
Figure 93. Dual-Footprint Analog Interface
149
Intel ® 82562ET / Intel ® 82562EH Dual Footprint Guidelines
149
Table 31. Intel ® 82562ET Operating States
149
815EG Chipset Platform Design Guide
150
Lpc/Fwh
151
In-Circuit FWH Programming
151
Fwh V
151
PP Design Guidelines
151
Figure 94. FWH VPP Isolation Circuitry
151
FWH Decoupling
152
Clocking
153
2-DIMM Clocking
153
Table 32. Intel CK-815 (2-DIMM) Clocks
153
Figure 95. Platform Clock Architecture for a 2-DIMM Solution
154
3-DIMM Clocking
155
Table 33. Intel CK-815 (3-DIMM) Clocks
155
Figure 96. Platform Clock Architecture for a 3-DIMM Solution
156
Clock Routing Guidelines
157
Figure 97. Clock Routing Topologies
157
Table 34. Simulated Clock Routing Solution Space
158
Clock Driver Frequency Strapping
159
Clock Skew Assumptions
160
Table 35. Simulated Clock Skew Assumptions
160
Intel ® CK-815 Power Gating on Wake Events
161
Power Delivery
163
Power Delivery Guidelines
163
Table 36. Power Delivery Definitions
163
Figure 98. Power Delivery Map
164
165
165
5V Dual Switch
165
Vddq
165
Vtt
165
3.3Vsb
166
Vcmos
166
Thermal Design Power
167
Pull-Up and Pull-Down Resistor Values
167
Figure 99. Pull-Up Resistor Example
167
ATX Power Supply PWRGOOD Requirements
168
Power Management Signals
168
Power Button Implementation
169
V/3.3 V Power Sequencing
170
Figure 100. Example 1.85 V/3.3 V Power Sequencing Circuit
170
V5REF/3.3 V Sequencing
171
Figure 101. V5REF/3.3 V Sequencing Circuitry
171
Power Plane Splits
172
Figure 102. Power Plane Split Example
172
Glue Chip 3 (ICH2 Glue Chip)
173
System Design Checklist
175
Design Review Checklist
175
Processor Checklist
175
GTL Checklist
175
CMOS Checklist
176
TAP Checklist for 370-Pin Socket Processors
176
Miscellaneous Checklist for 370-Pin Socket Processors
177
GMCH Checklist
178
System Memory Interface Checklist
178
Hub Interface Checklist
178
Digital Video Output Port Checklist
179
Intel ® ICH2 Checklist
179
PCI Interface
179
Hub Interface
179
LAN Interface
180
EEPROM Interface
180
FWH/LPC Interface
180
Interrupt Interface
180
GPIO Checklist
182
Usb
182
Power Management
183
Figure 103. USB Data Line Schematic
183
Processor Signals
184
System Management
184
Rtc
184
Figure 104. Intel ® ICH2 Oscillator Circuitry
185
Ac '97
185
Miscellaneous Signals
186
Figure 105. SPKR Circuitry
186
Power
187
Figure 106. V5REF Circuitry
187
IDE Checklist
188
Figure 107. Host/Device Side Detection Circuitry
189
Figure 108. Device Side Only Cable Detection
189
LPC Checklist
190
System Checklist
191
FWH Checklist
191
Clock Synthesizer Checklist
192
System Memory Checklist
193
Power Delivery Checklist
193
Third-Party Vendor Information
195
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