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General Information
teletypewriter and CRT control, diskette file system,
high-speed mathematics unit, and analog subsystems are
also available.
The development cycle of iSBC 80/30 based products
may be significantly reduced using an Intel Intellec
Microcomputer Development System. The resident
macroassembler, text editor, and system monitor greatly
simplify the design, development, and debug of iSBC
80/30 system software. An optional diskette operating
system provides -a relocating macro assembler, relocating
loader and linkage editor, and a library manager. A
unique In-Circuit Emulator (lCE-85) option provides the
capability of developing and debugging software directly
on the iSBC 80/30.
Intel's high level programming language, PL/M, is also
available as a resident Intellec Microcomputer Develop-
ment System option. PL/M provides the capability to pro-
gram in a natural, algorithmic language and eliminates the
need to manage register usage or allocate memory. PL/M
programs can be written in a much shorter time than
assembly language programs for a given application.
iSBC 80/30
1-4. EQUIPMENT SUPPLIED
The following are supplied with the iSBC 80/30 Single
Board Computer:
a.
Schematic diagram, d,wg no. 2002132
b.
Assembly drawing, dwg no. 1001576
1-5. EQUIPMENT REQUIRED
Because the iSBC 80/30 is designed to satisfy a variety of
applications, the user must purchase and install only those
components required to satisfy his particular needs. A list
of components required to configure all the intended
applications of the iSBC 80/30 is provided in table 2-1.
1-6. SPECIFICATIONS
Specifications of the iSBC 80/30 Single Board Computer
are listed in table 1-1.
Table 1-1. Specifications
WORD SIZE
Instruction:
Data:
CYCLE TIME:
MEMORY CAPACITY
On-Board ROMIE PROM:
1-4
On-Board RAM:
Off-Board Expansion:
MEMORY ADDRESSING
On-Board ROM/EPROM:
On-Board RAM
(CPU Access):
On-Board RAM
(Multibus Access):
8, 16, or 24 bits.
8 bits.
1.44 f.Lsec ±0.1 % for fastest executable instruction; i.e., four clock cycles.
Up to 8K bytes; user installed in 1 K, 2K, or 4K increments.
16K bytes of dynamic RAM; integrity maintained during power failure with user-
furnished batteries.
Up to 65K bytes of user-specified.combinations of RAM, ROM, and EPROM.
0-07FF (using 2708 or 2758 EPROM's or 8308 ROM's); O-OFFF (using 2716
EPROM's or 2316E ROM's); 0-1 FFF (using 2332 ROM's).
Jumpers allow on-board CPU to· access either 8K or 16K. For 8K RAM access,
addresses may be set on 8K boundaries 2000, 4000, ... EOOO. For 16K
access, addresses may be set on 16K boundaries 4000, 8000, or COOO. One
or both 8K segments may be reserved for CPU use only.
Jumpers allow board to act as slave for 8K or 16K RAM access by another
bus master; 16-bit or 20-bit addressing is accommodated and addresses are
irrespective of addresses used for CPU access. For 16-bit addrljssing, boundaries
may be set on any 8K or 16K segment of 65K byte address space. For 20-bit
addressing, boundaries may be set on any 8K or 16K segment of 1 M byte
address space.
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