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Principles of Operation
Figure 4-3 is presented to show the relationship between
an instruction cycle, machine cycle, and T-state. This
example shows the execution of a Store Accumulator
Direct (STA) instruction involving on-board memory.
Notice that for this instruction the opcode fetch (machine
cycle M
1 )
requires four T -states and the remaining three
cycles each require three T -states.
The opcode fetch is the only machine cycle that requires
more than three T -states. This is because the CPU must
interpret the req uirements of the opcode fetched during T
1
through T3 before it can decide what must be done in the
remaining T -state( s).
There are seven types of machine cycles, each of which
can be differentiated by the states ofthree CPU status lines
(lO/M, SO, and SI) and three CPU control lines (RD,
WR, and INT A). Table 4-1 lists the states of the CPU
status and control lines during each of the seven machine
cycles and during a CPU halt.
Table 4-1. CPU Status and Control Lines
Status
Control
Machine Cycle
101M
RD
WR
INTA
so
S1
Opcode Fetch
0
1
1
0
1
1
Memory Read
0
0
1
0
1
1
Memory Write
0
1
0
1
0
1
I/O Read
1
0
1
0
1
1
I/O Write
1
1
0
1
0
1
INTR Acknowledge
1
1
1
1
1
0
Bus Idle
X
X
X
1
1
1
Halt
TS
0
0
TS
TS
1
iSBC 80/30
4-19. OPCODE FETCH TIMING.
Figure 4-4 shows
the timing relationship of a typical opcode fetch machine
cycle. At the beginning ofT
1
of every machine cycle, the
CPU performs the following:
a.
Pulls IO/M low to signify that the machine cycle is a
memory reference operation.
b.
Drives status lines SO and S 1 high to identify the
machine cycle as an opcode fetch.
c.
Places high-order bits (PCH) of program counter
onto address lines A8-AI5. These address bits will
remain true until at least T
4.
d.
Places low-order bits (PCL) of program counter
onto address/data lines ADO-AD7. These address
bits will remain true for only one clock cycle, after
which ADO-AD7 go to their high-impedance state
as indicated by the dashed line in figure 4-3.
e.
Activates the Address Latch Enable (ALE) signal.
At the beginning of T
2,
the CPU pulls the RD/ line low to
enable the addressed memory device. The device will
then drive the ADO-AD7lines. After a period of time, as
determined by the access time of the addressed memory
device, valid data (the DCX instruction in this example)
will be present on the DO-D7 lines. During T3 the CPU
loads the data on the DO-D7 lines into its instruction
register and drives RD/ high, disabling the addressed
memory device. During T
4
the CPU decodes the opcode
and decides whether or not to enter T
5
on the next clock
cycle or start a new machine cycle and enter T
5
and then
T
6
before beginning a new machine cycle.
Figure 4-5 is identical to figure 4-4 with one exception,
which is the use of the READY input to the CPU. As
shown in figure 4-5, the CPU
e~amines
the state of the
I - + - - - - - - - - - - - - - - I N S T R U C T I O N C Y C l E - - - - - - - - - - - - - . . j
MACHINE
CYCLE
T STATE
ClK
TYPE OF
MACHINE CYCLE
ADDRESS BUS
MEMORY READ
MEMORY READ
MEMORY READ
MEMORY WRITE
THE ADDRESS (CONTENTS OF THE
THE ADDRESS (PC+ 1) POINTS THE ADDRESS (PC + 2) POINTS THE ADDRESS IS THE DIRECT
PROGRAM COUNTER) POINTS TO THE TO THE SECOND BYTE OF
TO THE THIRD BYTE OF THE
ADDRESS ACCESSED IN M2
FIRST BYTE (OPCODEI OF THE
THE INSTRUCTION
INSTRUCTION
AND M3
INSTRUCTION
DATA BUS
lOW ORDER BYTE OF THE
HIGH ORDER BYTE OF THE
CONTENTS OF THE
INSTRUCTION OPCODE (STA)
DIRECT ADDRESS
DIRECT ADDRESS
ACCUMULATOR
Figure 4-3. Typical CPU Instruction Cycle
4-4
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