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General Information
iSBC 80/30
Table 1-1. Specifications (Continued)
1-6
I/O ADDRESSING:
INTERFACE COMPATIBILITY
Serial I/O:
Parallel I/O:
Optional I/O:
INTERRUPTS:
COMPATIBLE CONNECTORS/CABLES:
ENVIRONMENTAL REQUIREMENTS
Operating Temperature:
Relative Humidity:
PHYSICAL CHARACTERISTICS
Width:
Depth:
Thickness:
Weight:
All communication to Parallel I/O and Serial I/O Ports, Timer, and Interrupt Controller
is via read and write commands from on-board 8085A CPU. Refer to table 3-2.
EIA Standard RS232C signals provided and supported:
Carrier Detect
Receive Data
Clear to Send
Ring Indicator
Data Set Ready
Secondary Receive Data
Data Terminal Ready
Secondary Transmit Data
Request to Send
Transmit Clock
Receive Clock
Transmit Data
24 programmable lines (8 lines per port); one port includes bidirectional bus driver.
IC sockets included for user installation of line drivers and/or I/O terminators as
required for interface ports. Refer to table 2-1.
IC socket included for Intel 8041/8741 Universal Peripheral Interface (UPI). Also
included are IC sockets for user installation of line drivers and/or I/O terminators as
required for interface. Refer to table 2-1.
8085A CPU includes five interrupt inputs, each of which vectors processor to the
following unique memory locations for entry point to service routine:
Interrupt
Vector
Priority
Type
Input
Address
TRAP
24H
Highest
Non-maskable
RST 7.5
3CH
t
Maskable
RST 6.5
34H
Maskable
RST 5.5
2CH
Maskable
INTR
Note
Lowest
Maskable
Note: INTR input provided by 8259A PIC, which is programmable to pro-
vide vector CALL address of service routine for interrupting device.
Jumpers allow selection of 12 priority interrupts from 18 interrupt sources. PIC may
be programmed to respond to edge-sensitive or level-sensitive inputs.
Refer to table 2-2 for compatible connector details. Refer to paragraphs 2-29 and
2-30 for recommended types and lengths of I/O cables.
To 90% without condensation.
30.48 cm (12.00 inches).
17.15 cm (6.75 inches).
1.27 cm (0.50 inch).
425 gm (15 ounces).
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