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iSBC 80/30
4-23. I/O WRITE TIMING.
Figure
4-7
also illustrates
the timing of two successive
VO
write machine cycles, the
first without a T
wait
state and the second with one T
wait
state. With the exception of the
101M
status signal, the
timing of a memory write cycle and an
VO
cycle are
identical.
4-24. INTERRUPT
ACKNOWLEDGE
TIM-
ING.
Figure
2-8
shows the CPU timing in response to the
INTR input being driven high by PIC A30 (assuming the
CPU interrupt enable flip-flop has been set by a pre-
viously executed Enable Interrupt instruction). The status
of the TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR
inputs are sampled during CLK of the T -state im-.
mediately preceding T
1
of M
1.
If INTR was the only valid
interrupt, the CPU clears its interrupt enable flip-flop and
enters the Interrupt Acknowledge (INA) machine cycle.
With two exceptions, the INA machine cycle is identical
with the Opcode Fetch (OF) machine cycle. The first
exception is that
101M
=
1, which signifies that the
opcode fetched will be from an
VO
device. The second
exception is that INT A is asserted instead of RD. Al-
though the contents of CPU program counter is sent out on
the address lines, the address lines are ignored.
When INTA is asserted, the PIC provides a CALL instruc-
tion which causes the CPU to push the contents of the
MWOR lOW
SIGNAL
T,
T2
T3
-
LI
~
L.t
elK
-
ex
101M,
101M - 0 (MWI OR 1 (lOWI, SI "0, SO· 1
S1,SO
i -
~
D<
AIfA '5
~
OUT
OUT
~
ex
AO O ·A0 7
AO-A7
0 0 .0 7
~
ALE
V\
~
WR
READY
L -
~
Principles of Operation
program counter onto the stack before jumping to a new
location. After receiving the CALL opcode, the CPU
perform a second INA machine cycle (M 2 ) to access the
second byte of the CALL instruction from the PIC. The
timing of M2 is identical with M
1
except that M2 has three
T-states. M2 is followed by M3 to access the third byte of
the CALL instruction. When all three bytes have been
received, the CPU executes the instruction. The CPU
inhibits the incrementing of the program counter during
the three INA cycles so that the correct program counter
value can be pushed onto the stack during M4 and M
5 .
During M4 and M
5 ,
the CPU performs Memory Write
(MW) machine cycles to write (push) the contents of the
program counter onto the top of the stack. The CPU then
places the two bytes accessed during M2 and M3 into the
upper and lower bytes of the program counter. This has
the same effect as jumping the execution of the program to
the location specified by the CALL instruction.
After the interrupt service routine is executed, the CPU
pops the stack and loads it into the program counter, and
resumes system operation at the point of the interrupt. (It
is the programmer's responsibility to ensure that the inter-
rupt enable flip-flop is set before returning from the ser-
vice routine.)
MWOR lOW
T,
T2
TWA IT
T3
LI
L I
l.....r-
L J
'-
:
IO/M·O (MWI OR 1 (lOWI, SI " 0,
sq
a
1
)
)
OUT
OUT
AO·A7
°0·°7
)
v---\
V-
r
~
'L
""' "
~
~
..
Figure 4-7. Memory Write (or 1/0 Write) Machine Cycles
4-7
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