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iSBC 80/30
Programming Information
Table 3-16. Typical PPI Port Write Subroutine
;COUT OUTPUTS A BYTE FROM REG A TO PORT C.
;USES-A; DESTROYS-NOTHING.
COUT:
OUT
OEAH
RET
END
ity interrupts will be able to generate an interrupt that will
be acknowledged if the CPU has enabled its own interrupt
'input through software. An End-Of-Interrupt (EOI) com-
mand from the CPU is required to reset the PIC for the
next interrupt.
3-37. AUTO-ROTATING MODE.
In this mode the
interrupt priority rotates. Once an interrupt on a given
input is serviced, that interrupt assumes the lowest priori-
ty. Thus, if there are a number of simultaneous interrupts,
the priority will rotate among the interrupts in numerical
order. For example, if interrupts IR4 and IR6 request
service simultaneously, IR4 will receive the highest prior-
ity. After service, the priority level rotates so that IR4 has
the lowest priority and IRS assumes the highest priority.
In the worst case, seven other interrupts are serviced
before IR4 again has the highest priority. Of course, ifIR4
is the only request, it is serviced promptly. In the Auto-
Rotating Mode, priority shifts when the PIC chip receives
an End-of-Interrupt (EOI) command.
3-38. SPECIFIC ROTATING MODE.
In this mode
the software can change interrupt priority by
~pecifying
the bottom priority, which automatically sets the highest
priority. For example, if IRS is assigned the bottom prior-
ity, IR6 assumes the highest priority. In the specific rotat-
CONTROL WORD
BIT SET/RESET
1· SET
O· RESET
L . . . . . - - - - - - - - - - _ I
~I! ;~:g~~SET
FLAG
Figure 3-12. PPI Port C Bit Set/Reset Control
Word Format
ing mode, the priority can be rotated by writing a Specific
Rotate at EOI (SEOI) command to the PIC chip. This
command contains the BCD code of the interrupt being
serviced; that interrupt is reset as the bottom priority. In
addition, the bottom priority interrupt can be fixed at any
time by writing a command word to the PIC chip.
3-39. INTERRUPT MASK
One or more of the eight interrupt request inputs can be
individually masked during the PIC initialization or at any
subsequent time. If an interrupt is masked while it is being
serviced, lower priority interrupts are inhibited. There are
two ways to enable the lower priority interrutps:
a.
Write an End-of-Interrupt (EOI) command.
b.
Set the Special Mask Mode.
The Special Mask Mode is useful when one or more
interrupts are masked. If for any reason an input is masked
while it is being serviced, the lower priority interrupts are
disabled. However, it is possible to enable the lower
priority interrupt with the Special Mask Mode. In this
mode, the lower priority lines are enabled until the Special
Mask Mode is reset. Higher priorities are not affected.
3-40. STATUS READ
Interrupt request inputs is handled by the following two
internal PIC registers:
a.
Interrupt Request Register (lRR) , which stores all
interrupt levels that are requesting service.
b.
In-Service Register (lSR), which stores all interrupt
levels that are being serviced.
Either register can be read by writing a suitable command
word and then performing a read operation.
3-41. INITIALIZATION COMMAND WORDS
The eight devices serviced by the PIC have eight
addres~
ses equally spaced in memory that can be programmed at
intervals of four or eight bytes. Interrupt service routines
for these eight devices thus occupy a 32- or64-byte block,
respectively, of memory. The address format for device
interrutp service routine is shown in figure 3-13.
3-15
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