Signal Descriptions; Clock (Clk); Address Bus (A[31:2], Be[3:0]#); Functional Signal Groupings - Intel Quark SoC X1000 Core Developer's Manual

Figure 69.

Functional Signal Groupings

9.2

Signal Descriptions

9.2.1

Clock (CLK)

CLK provides the fundamental timing and the internal operating frequency for the
®
Intel Quark SoC X1000 Core. All external timing parameters are specified with respect
to the rising edge of CLK.
9.2.2

Address Bus (A[31:2], BE[3:0]#)

A[31:2] and BE[3:0]# form the address bus and provide physical memory and I/O port
addresses. The Intel
physical memory space (00000000H through FFFFFFFFH), and 64 Kbytes of I/O
®
Intel Quark SoC X1000 Core
Developer's Manual
150
®
Quark SoC X1000 Core is capable of addressing 4 gigabytes of
®
Intel Quark Core—Hardware Interface
Order Number: 329679-001US
October 2013