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Principles of Operation
4-8. UNIVERSAL PERIPHERAL
INTERFACE
The optionafS041/8741A Universal Peripheral Interface
(UPI) is a complete single chip microcomputer that inter-
faces directly to the 808SA CPU through the I/O structure.
The UPI can interface devices such as a printer controller
or a keyboard scanner while relying on the CPU only for
data transfer.
4-9. INTERRUPT CONTROL
The interrupt section provides 12 priority interrupts. Eight
interrupts connect to the inputs of the 8259 Programmable
Interrupt Controller (PIC);. the" remaining four interrupts
connect directly to the 8085A CPU. All interrupts, except
TRAP, are maskable;. the TRAP interrupt is intended to
handle a power fail (PFI/) signal input via auxiliary con-
nector P2.
There are 18 jumper-selectable interrupt sources: PPI (2),
UPI (1), USAR T (2), PIT (2), external via 11 and J2 (2),
power fail via P2 (1), and Multibus (8).
4-10~
ROM/EPROM CONFIGURATION
IC sockets A25 and A37 are provided for user installation
of ROM/EPROM chips. Jumpers are provided to accom-
modate either lK, 2K, or 4K chips. The on-board ROM/
EPROM address space begins at 0000. This space is
normally reserved for ROM/EPROM use only; however,
ROMiEPROM may be disabled through an optional
jumper connect on the 8255A PPI output port.
4-11. RAM CONFIGURATION
The iSBC 80/30 includes 16K of dynamic RAM im-
plemented with eight Intel 2117 chips and an Intel 8202
Dynamic RAM Controller. Dual-port control logic inter-
faces this RAM with the Multibus so that the iSBC 80/30
can perform as a slave RAM device when not acting as a '
bus master. The slave RAM decode logic allows
exte~ded
Multibus addressing of up to 20 address lines. This allows
bus masters with 20-bit addressing capability to partition
the iSBC 80/30 into any 8K or 16K segment in a
I-megabyte address space. The 8085A CPU, however,
has only a 16-bit address capability and the 16K RAM
must reside in a 64K address space. Hardware jumpers
allow the 8085A CPU or the system to access either 8K or
16K of on-board RAM.
4-12. BUS INTERFACE
The interface to the Multibus includes an Intel Bus Con-
troller, bidirectional address and data bus drivers, and the
bus interrupt driver/receivers. The bus controller allows
the is:t:3C 80/30 to operate as a bus master in a serial or
parallel priority arrangement with other bus masters in the
system in which the 8085A CPU can request the Multibus
only when a bus resource is needed.
4-2
iSBC 80/30
4-13. DUAL PORT CONTROL
The dual-port control logic allows the iSBC 80/30 to
function as a slave RAM device when not acting as a bus
master. The dual-port control logic enables or disables the
internal data and address buses, depending on whether the
access is from the 8085A CPU or from the Multibus. For
RAM access, the 8085A CPU has priority over a Multibus
request.
An extended addressing facility is provided to allow the
16K RAM to reside within a I-megabyte address space
when accessed from the Multibus. This is useful when one
or more bus masters have a 20-bit addressing capability.
The 8085A CPU, however, can only access this memory
in the lowest 64K address space.
4-14. CIRCUIT ANALYSIS
The schematic diagram for the iSBC 80/30 is given in
figure 5-2. The schematic diagram consists of nine sheets,
each of which includes grid coordinates. Signals that
transverse from one sheet to another are assigned grid
coordinates at both the signal source and signal destina-
tion. For example, the grid coordinates 2ZBl locate a
signal source (or signal destination as the case may be) on
sheet 2 Zone B 1.
Both active-high and active-low signals are used. A signal
mnemonic that ends with a virgule (e.g., DAT7/) denotes
that the signal is active low (=50.4 V). Conversely, a
signal mnemonic without a virgule (e.g., ALE) denotes
that the signal is active high
(~2.0V).
Figures 4-1 and 4-2 at the end of this chapter are
simplified block diagrams of the input/output, interrupt,
and memory sections. These block diagrams will be help-
ful in understanding both the addressing scheme and the
internal bus structure of the board.
4-15. INITIALIZATION
When power is applied in a start-up sequence, the con-
tents of the 8085A CPU program counter, instruction
register, and interrupt enable flip-flop are subject to ran-
dom factors' and cannot be predicted. For this reason, a
power-up sequence is used to set the CPU, bus controller,
and I/O ports to a known internal state.
When power is initially applied to the iSBC 80/30,
capacitor C7 (7ZA 7) begins to charge through resistor R2.
The charge developed across C7 is sensed by a Schmitt
trigger, which is internal to Clock Generator A13. The
Schmitt trigger converts the slow transition appearing at
pin 2 into a clean, fast-rising synchronized RESET output
signal at pin 1. The RESET signal is inverted by A29-11
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