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iSBC 80/30
Programming Information
Table 3-9. Typical PIT Count Value Load Subroutine
;LOADO LOADS COUNTER 0 FROM D&E,D IS MSB, E IS LSB.
;USES-D,E; DESTROYS-A.
3-20. OPERATION
LOADO: MOV
OUT
MOV
OUT
RET
END
A,E
ODC
A,D
ODC
The following paragraphs describe operating procedures
for a counter read, clock frequency divider/ratio selec-
tion, and interrupt timer count selection.
3-21. COUNTER READ. There are two methods that
can be used to read the contents of a particular counter.
The first method involves a simple read of the desired
counter. The only requirement with this method is that, in
order to ensure a stable count reading, the desired counter
must be inhibited by controlling its gate input. Only
Counter 0 and Counter 1 can be read using this method
because the gate input to Counter 2 is not controllable.
The second method allows the counter to be read "on-
the-fly." The recommended procedure is to use a mode
control word to latch the contents of the count register;
this ensures that the count reading is accurate and stable.
The latched value of the count can then be read.
NOTE
If a counter is read during count, it is mandatory
to complete the read procedure; that is, if two
bytes were programmed to the counter, then
two bytes must be read before any other opera-
tions are performed with that counter.
To read the count of a particular counter, proceed as
follows (a typical counter read subroutine is given in table
3-10):
;GET LSB
;GET MSB
a.
Write counter register latch control word (figure
3-10) to DF. Control word specifies desired counter
and selects counter latching operation.
b.
Perform a read operation of desired counter; refer to
table 3-2 for counter addresses.
NOTE
Be sure to read one or two bytes, whichever
was specified in the initialization mode control
word. For two bytes, read in the order specified.
3-22. CLOCK FREQUENCY IDIVIDE RATIO
SELECTION. Table 2-4 lists the default and optional
timer input frequencies to Counters 0 through 2. The timer
input frequencies are divided by the counters to generate
the 8041/8741 Event Clock (Counter 0), Count Out
(Counter 1), and the 8251A Baud Rate Clock (Counter2).
Each counter must be programmed with a downcount
number, or count value N. When count value N is loaded
into a counter, it becomes the clock divisor. To derive
N
for either synchronous or asynchronous RS232C opera-
tion, use the procedures
describ~d
in following
paragraphs.
3-23. Synchronous Mode. In the synchronous mode, the
TXC and/or RXC rates equal the Baud rate. Therefore,
the count value is determined by
N
=
C/B
Table 3-10. Typical PIT Counter Read Subroutine
;READ1 READS COUNTER 1 ON-THE-FL Y INTO D&E. MSB IN D, LSB IN E.
;USES-NOTHING; DESTROYS-A,D,E.
READ1: MVI
OUT
IN
MOV
IN
MOV
RET
END
A,40H
ODF
ODD
E,A
ODD
D,A
;MODEWORD FOR LATCHING COUNTER 1 VALUE
;LSB OF COUNTER
;MSB OF COUNTER
3-11
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