Intel iSBC 80 Hardware Reference Manual page 63

iSBC 80/30 Programming Information
Table 3-23. Typical PIC Mask Register Read Subroutine
;RMASK READS PIC MASK REGISTER.
;USES-NOTHING; DESTROYS-A.
RMASK: IN
RET
END
GOgH
Table 3-24. Typica! PIC End-of-Interrupt Command Subroutine
;EOI ISSUES END-OF-INTERRUPT TO PIC.
;USES-NOTH ING; DESTROYS-A.
EOI:
NOTE
MVI
OUT
RET
END
The data bus buffer configuration does not
allow the CPU to read back data it has previously
written into the data bus buffer register. Also,
the UPI cannot input data from the data bus
buffer register that it previously output. The
CPU can only read data that the UPI has output
and the UPI can only input data that the CPU has
written.
8041/8741
A,2GH
GD8H
(4)
STATUS
REGISTER
DATA BUS
DATA
BUS BUFFER
REGISTER
;NON-SPECIFIC EOI
The 4-bit status register indicates-the status of the data bus
buffer register and implements the handshaking protocol
required for two-way data transfer. The four bits compris-
ing the status register are defined as follows:
a. Bit 0: Output Buffer Full. The OBF flag is auto-
matically set when the UPI loads the data bus buffer
register and cleared when the CPU reads the data
bus buffer register.
STATUS FLAG DEFINITION:
OBF OUTPUT BUFFER FULL FLAG
IBF INPUT BUFFER FULL FLAG
Fl CONTROL/DATA ,FLAG
FO GENERAL FLAG
CONTROL SIGNAL DEFINITION:
WR WR ITE STROBE
RD READ STROBE
CS
CHIP SELECT
AO ADDRESS INPUT
Figure 3-16. UPI Data Bus Buffer and
Status Registers
3-21