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CHAPTER
4·
PRINCIPLES OF OPERATION
4-1.
INTRODUCTION
This chapter provides a functional description and a cir-
cuit analysis of the iSBC 80/30 Single Board Computer.
Figures 4 -1 and 4 -2, located at the end of this chapter, are
simplified foldout block diagrams that illustrate the func-
tional interface between the 8085A microprocessor
(CPU) and the on-board facilities and between the CPU
and the system facilities via the Multibus. Also shown in
figure 4-2 is the dual port control logic that allows the
iSBC 80/30 to function in a master/slave relationship with
the Multibus to allow another bus master to access the
on-board RAM.
4-2.
FUNCTIONAL DESCRIPTION
A brief description of the functional blocks comprising
the iSBC 80/30 is given in following paragraphs. An
operational circuit analysis is given beginning with parag-
raph 4-14.
4-3. CLOCK CIRCUITS
The clock circuit composed of A12, A13, and A21 is
stabilizedby a 22.1184-MHz crystal. This circuit, which
provides the various clock frequencies required for on-
board activities, generates a power-up Reset signal to
initialize the system to a known internal state; a Reset
signal can also be initiated by a signal supplied via aux-
iliary connector P2.
The clock circuit composed of A55 and A57 is stabilized
by an 18.432-MHz crystal. This frequency is divided by
two to provide the 9.22-MHz Bus Clock (BCLK/) and
Constant Clock (CCLK/) to the Multibus. (The BCLK/
signal is also used by B us Controller A67 .) Removable
jumpers are provided to allow this on-board clock circuit
to be disabled if some other source supplies BCLK/ and
CCLK/ to the Multibus.
4-4. CENTRAL PROCESSOR UNIT
The,8085A Microprocessor (CPU), which is the heart of
the single board computer, performs system processing
functiqns and generates the address and control signals
required to access memory and
VO
devices. The ADO-
AD7 pins are used to multiplex the 8-bit input!output data
and the lower eight bits of the address. During the first
part of a machine cycle, for example, the lower eight bits
of address are strobed into Latch A23 by the Address
Latch Enable (ALE) signal; the outputs of A23 are com-
bined with the upper eight bits of the address to form the
16-bit address bus. During the remainder of the machine
cycle, ADO-AD7 pins of the CPU are used for data input!
output.
4-5. INTERVAL TIMER
The 8253 Programmable Interval Timer (PIT) includes
three independently controlled counters that provide op-
tional (jumper selectable) timing inputs to the on-board
VO
devices and the CPU interrupts. The clock frequency
of2.46 MHz, 1.23 MHz, or 153.6 kHz, which is derived
from the clock circuit composed of A12, A13, and A21,
provides the basic timing input.
Counter 2 provides timing for the serial
VO
port (8251 A
USART). This counter, in conjunction with the USART,
can provide programmable Baud rates from 110 to 9600.
Counter 0 can be used as a timing input to the optional
8041/8741 UPI which, in tum, can connect this signal to
its own internal timer input. Counter 0, if not employed by
an optional UPI, can be used as an interval timer to
generate a CPU interrupt. Counter 1, which is the system
interval timer and can also generate a CPU interrupt, has a
range of 1.6 microseconds to 853.3 milliseconds. If
longer times are required, Counters 0 and 1 can be cas-
caded to provide a single timer with a maximum delay of
more than 50 hours.
4-6. SERIAL I/O
The 8251A Universal Synchronous/Asynchronous
Receiver/Transmitter (USART) provides RS232C com-
patibility and is configured as a data terminal. Synchron-
ous or asynchronous mode, character size, parity bits,
stop bits, and Baud rates are all programmable. Data,
clocks, and control lines to and from connector J3 are
buffered with drivers and receivers.
A second serial
VO
channel may be derived from prog-
ramming the optional 8041/8741 UPI to simulate the
USAR T. This second channel is limited in speed and the
number of RS232C interface lines (one driver and one
receiver) but is sufficient to communicate with a simple
CRT interface.
4-7. PARALLEL I/O
The 8255A Programmable Peripherel Interface provides
24 programmable
VO
lines. A bidirectional bus driver is
included to interface eight of the
VO
lines to connector
n.
Two IC sockets are provided so that, depending on the
application, TTL drivers or
VO
terminators may be instal-
led to complete the interface to connector
n.
The 24 lines
are grouped into three ports of eight lines each; these ports
can be programmed to be &imple
VO
ports or strobed
VO
ports with handshaking. One port can be programmed as a
bidirectional port with control lines. The iSBC 80/30
includes various optional features such as RS232C inter-
face lines, timer gates, and interrupts that can be control-
led by the parallel
VO
lines.
4-1
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