Operation Command Words; Addressing; Initialization; Operation - Intel iSBC 80 Hardware Reference Manual

Programming Information
~ 0 ' 6
Os
0 4
0 3
O 2 0 1
Do
A7
I
A6
I
As A4 A3 A2 Al AO
I
'---.---l- - -
j \
v
)
DEFINED BY 05-7 OF ICW'
AUTOMATICAllY
INSERTED BY 8259
~~--------------v~------------~)
DEFINED BY ICW2
Figure 3-13. PIC Device Interrupt Addresses
Bits 0-4 are automatically inserted by the PIC whereas bits
6-15 are programmed by Initialization Command Words
ICWI and ICW2. If the address interval is eight bytes, bit
5 is automatically inserted by the PIC; if the address
interval if four bytes, bit 5 is programmed in ICWI. Thus,
the 32-byte or 64-byte block of addresses reserved for
interupt service routines can be located anywhere in the
available memory space. Table 3-17 shows the address
format inserted by the PIC for each device.
Initialization of the PIC consists of writing two or three
8-bit Initialization Command words as shown in figure
3 -14. Since there are no slave PIC's, the initialization for
the one PIC consists of writing two Initialization Com-
mand Words as follows:
a. The first Initialization Command Word (lCW1) con-
sists of the following:
(1)
Bits 5-7 specify the most-significant bits of the
lower address byte of the interrupt service
routine.
(2) Bit 3 establishes whether the interrupts are re-
quested by a positive-true or requested by a
low-to-high transition input. This applies to all
input requests handled by the PIC. In other
words, if bit 3-1, a low-to-high transition is
required to request an interrupt on any of the
eight levels ,handled by the PIC.
(3) Bit 2 specifies a 4-byte or 8-byte address
interval.
iSBC 80/30
(4) Bit 1 specifies whether or not there are slave
(cascaded) PIC's. Since there are no slave PIC's,
set bit 1
==
l.
(5) Bits 0 and 4 identify the word as ICWl.
b. The second word (lCW2) specifies the upper byte
(bits 8-15) of the interrupt service routine.
3-42. OPERATION COMMAND WORDS
After being initialized, the PIC can be programmed at any
time for various interrupt modes. The Operation Com-
mand Word (OCW) formats are shown in figure 3-15 and
discussed in paragraph 3 -45.
3-43. ADDRESSING
The PIC uses two consecutive addresses for writing to and
reading internal registers. Address functions pertinent to
programming are identified in table 3 -2.
3-44. INITIALIZATION
To initialize the PIC, proceed as follows (table 3-17
provides a typical initialization subroutine);
a. Disable system interrupts by executing a DI (Disable
Interrupts) instruction.
b. Write ICWI to D8.
c. Write ICW2 to D9.
d.' Enable system interrupts by executing an EI (Enable
Interrupts) instruction.
NOTE
The PIC operates in the fully nested mode after
the initialization sequence without requiring any
Operation Control Word (OCW).
3-45. OPERATION
After initialization, the PIC chips can be progr~mmed at
any time for the following operations:
Table 3-17. PIC Device Address Insertion
Device
Lower Routine Address Byte
Interval
=
4
Interval
=
8
D7 D6
D5 .D4 D3 D2 Dl DO
D7 D6
D5
D4 D3 D2
Dl DO
IR7
A7 A6 A5 1
1 1
0 0
A7 A6 1 1 1
0 0 0
IR6
A7 A6
A5 1 1
0 0 0
A7
A6
1 1
0 0 0
0
, IR5 A7 A6 A5 1
0
1
0
0 A7 A6
1
0
1
0 0 0
IR4 A7 A6
A5 1
0
0 0 0
A7 A6 1
0 0 0 0 0
IR3 A7 A6
A5
0
1 1
0 0
A7 A6
0
1 1
0 0 0
IR2 A7
A6 A5
0
1
0 0 0
A7 A6
0
1
0 0 0 0
IR1 A7
A6 A5
0
0
1
0 0
A7 A6
0 0
1
0 0 0
IRO
A7 A6 A5
0
0 0 0 0
A7 A6
0 0 0
0
0 0
3-16