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1-1. INTRODUCTION
The iSBC 80/30 Single Board Computer, which is a
member of Intel's complete line of iSBC 80 computer
products, is a computer system on a single printed-
circuit assembly. The iSBC 80/30 includes a central pro-
cessor unit (CPU), 16K bytes of dynamic random access
memory (RAM), one serial and three parallel I/O ports,
a programmable
timer~
priority interrupt logic, and Multi-
bus control logic. Also included is dual port control logic
to allow the iSBC 80/30 to act as a slave RAM device
to other bus masters in the system. Provision is made
for user-installation of masked or programmable read
only memory (ROM or EPROM) and an Intel 8041 or
8741A Universal Peripheral Interface.
1-2. DESCRIPTION
The iSBC 80/30 Single Board Computer (figure 1-1) is
controlled by an Intel 8085A Microprocessor (CPU),
which includes six 8-bit general-purpose registers and an
accumulator. The six general-purpose registers may be
addressed individually or in pairs, which allows both
single precision and double precision operations. The
CPU has a 16-bit program counter which allows direct
CHAPTER 1
GENERAL INFORMATION
addressing of up to 65K of memory. An external stack,
located within any portion of read/write memory, may be
used as a last-in/first-out storage area for the contents of
the program counter, flags, accumulator, and all six
general-purpose registers. A 16-bit stack pointer controls
the addressing of this external stack, which allows sub-
routine nesting that is bounded only by the 65K address
limitation.
The iSBC 80/30 has an internal bus for all on-board
memory and I/O operations and accesses the system bus
(Multibus) for all external memory and I/O operations.
Hence, local (on-board) operations do not involve the
Multibus and allow true parallel processing when several
bus masters (e.g., DMA devices and other single board
computers) are used in a multimaster scheme.
The 16K of dynamic RAM is implemented with eight Intel
2717 chips and an Intel 8202 Dynamic RAM Controller.
Dual port control logic is included to interface this 16K
RAM with the Multibus so that the iSBC 80/30 can func-
tion as a slave RAM device when not in control of the
Multibus. The CPU has priority when accessing on-board
RAM. After the CPU completes its read or write opera-
tion, the controlling bus master is allowed to access RAM
and complete its operation. Where both the CPU and the
controlling bus master have the need to write or read
PARALLEL
1/0
OPTIONAL
8041/8741
1/0
SERIAL
1/0
(MULTIBUS)
(AUXILIARY)
611-1
Figure 1-1. iSBC 80/30 Single Board Computer
1-1
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