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iSBC 80/30
Preparation for Use
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Figure 2-4. Bus Exchange Timing (Slave Mode)
2-26. SERIAL PRIORITY RESOLUTION
In a multiple bus master system, bus contention can be
resolved in an iSBC 604 Modular Backplane and Card-
cage by implementing a serial priority resolution scheme
as shown in figure 2-5. Due to the propagation delay of
the BPRO/ signal path, this· scheme is limited to a
maximum of three bus masters capable of acquiring and
controlling the Multibus. In the configuration shown in
figure 2-5, the bus master installed in slot J2 has the
highest priority and is able to acquire control of the
Multibus at any time because its BPRN/input is always
enabled (tied to ground) through jumpers Band N on the
backplane. (See figure 5-3.)
If the bus master in slot J2 desires control of the Multibus,
it drives its BPRO/ output high and inhibits the BPRN/
input to all lower-priority bus masters. When finished
using the Multibus, the J2 bus master pulls its BPRO/
output low and gives the 13 bus master the opportunity to
take control of the Multibus. If the 13 bus master does not
2-23
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