Interrupt Operation - Intel iSBC 80 Hardware Reference Manual

iSBC 80/30
A72/A73 to the RAM Controller. When the Dual Port
Control logic asserts the OFF BD CS/ signal, the RAM
Controller PCS/ input is enabled and, depending on which
command has been asserted (RAMRD/ or RAMWRT/),
drives the WEI input high to RAM.
The RAM Controller generates SACK! and XACK/ as
previously described. For a bus access, the SACK/ signal
develops SLA VE AACK/ and XACK! develops SLA VE
XACK/. The controlling bus master then drives the
Principles of Operation
MRDC/ or MWTC/ command hIgh and deactivates ad-
dress drivers A 72/ A 73.
4-43. INTERRUPT OPERATION
All interrupts except INTR are connected to the CPU by
jumper connections. (Refer to paragraph 2-20.) Since
interrupt handling is handled by the internal CPU timing
described in paragraph 4-24, no further explanation is
considered necessary.
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