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iSBC 80/30
If the hardware generates a TRAP interrupt on power up or
power fail, the system must be able to process the TRAP
interrupt before it is completely initialized. It should also
take into account that an interrupt routine that runs with
interrupts disabled can still be interrupted by a TRAP.
Because of these considerations, it is recommended that
the TRAP interrupt only be used for system startup and/or
catastrophic error handling.
It should be noted that TRAP does not destroy a previ-
ously established interrupt enable status. Executing the
first RIM instruction followip.g a TRAP interrupt yields
the interrupt enable status as it was before the TRAP
occurred. Following this first mandatory RIM instruction,
subsequently executed RIM instuctions provide current
interrupt enable status.
3-49. RST 7.5, 6.5, 5.5 INPUTS
These interrupts can be individually masked by a SIM
instruction and 'can thus be prevented from interrupting
the CPU. The priorities shown in table 3-27 does not take
into account the priority of a routine that was started by a
higher priority interrupt. An RST 5.5 interrupt can inter-
rupt an RST 7.5 routine if the interrupts are re-enabled
before the end of the RST 7.5 routine.
The RST 6.5 and 5.5 interrupts are high level sensitive
and, in order to be recognized, must remain high. The
Programming Information
RST 7.5 interrupt is rising edge sensitive and only a pulse
is required to set the interrupt request; this request will be
remembered until the request is serviced or reset by a SIM
instruction.
The TRAP interrupt, which is both edge and level sensi-
tive, must have a leading (positive-going) edge and then
remain high until serviced.
3-50. INTR INPUT
The INTR input from the 8259A PIC has the lowest
priority and is sampled only during the last clock cycle of a
given instruction. When INTR is active, the CPU Prog-
ram Counter (PC) is inhibited and three bytes, timed by
INTN pulses, are transferred from the PIC to the CPU:
a. Byte 1
=
CALL instruction (11001101)
b. Byte 2
=
Lower byte of routine address
c. Byte 3
=
Upper byte of routine address.
The 16-bit routine address must be on a 32-byte boundard
or 64-byte boundary as determined by the Initialization
Command Words previously written to the PIC. (Refer to
paragraph 3-41.)
The INTR is enabled or disabled by software. It is dis-
abled by "reset" and immediately after an interrupt is
accepted.
3-23/3-24
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