Intel iSBC 80 Hardware Reference Manual page 34

iSBC 80/30
Preparation for Use
Table 2-15. iSBC 80/30 AC Characteristics (Master Mode)
Overall Read Write
Parameter
Min. Max. Min. Max. Min. Max.
(ns) (ns) (ns) (ns) (ns) (ns)
Description
Remarks
tAS
50 50 50
Address setup time to command
tAH
50 50 50
Address hold time from command
tos
50 50
Data setup to command
tOHW
50 50
Data hold time from command
.tCY
358 365
CPU cycle time
tCMoR
670
Read command width
With
1
wait state
tCMOW
390
Write command width With
1
wait state
tCSWR
575
Read-to-write command separation
In override mode
tCSRR
465
Read-to-read command separation
In override mode
tcsww
575 Write-to-write command separation In override mode
tCSRW
465
Write-to-read command separation
In override mode
tXACK1
-195
Read command to XACK
1 st sample point In override mode
tXACK2
-509 Write command to XACK
1
st sample point In override mode
tSAM
350 375
Time between XACK samples In override mode
tACKRO
75
AACK to valid read data
When AACK is used
tACKWT
175 AACK to write command inactive When AACK is used
tOHR
0 Read data hold time
tOXL
-75 Read data setup to XACK
tXKH
0 0 0
XACK hold time
tsw
35
Bus clock low or high interval
Supplied by system
tss
23
BPRN to BCLK setup time
toSY
55
BCLK to BUSY delay
tNOO
30
BPRN to BPRO delay
tsCY
108 109
Bus clock period (BCLK)
From iSBC
80/30
when terminated
tsw
35 74
Bus clock low or high interval
From iSBC
80/30
when terminated
tlNIT
3000
Initialization width
After all voltages have stabilized
Table 2-16. iSBC 80/30 AC Characteristics (Slave Mode)
Parameter
Minimum Maximum
Description
Remarks
(ns) (ns)
tAS
50
Address setup to command
From address to command
tos
-200
Write data setup to' command
tOS1
1500
On-board memory cycle delay
No refresh
tACK
480
720 Command to XACK
tCMo
720
Command width
tAH
0
Address hold time
tOHW
0
Write data hold time
tOHR
0 Read data hold time
tXTH
0 45
Acknowledge hold time
Acknowledge turnoff delay
*tACC
645
Access time to read data
tlH
50 Inhibit time from command trailing edge Blocks AACK if tiS> tiS min.
tlPW
100
Inhibit pulse width
*tCY
680 920
Minimum cycle time tCY =. tACK
+
tSEP
toS2
1865 On board memory cycle delay
Refresh delaying SACK
tRO
535 555 Refresh delay time
toxL
25
Read data setup to XACK
tsEP
200
Command separation
tiS
-50
Inhibit setup to command
Blocks RAM cycle and tACK
*When an asynchronous refresh cycle occurs, tRO is added to these parameters; when on-board memory cycle occurs, tOS1 is
also added.
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