Universal Peripheral Interface; Line Drivers And I/O Terminators; Rise Time/Noise Capacitors; Jumper Configuration - Intel iSBC 80 Hardware Reference Manual

Preparation for Use
The default (factory connected) jumpers are configured
for Intel 2316E ROM or 2716 EPROM. If different type
chips are installed, reconfigure the jumpers as described in
paragraph 2 -14.
2-10. UNIVERSAL PERIPHERAL
INTERFACE
Install the optional Inte18041/8741A Universal Peripheral
Interface (UPI) chip in socket A20. (Refer to figure 5-1
zone ZC6 and figure 5-2. zone 5ZC4.)
2-11. LINE DRIVERS AND 110
TERMINATORS
Table 2-3 lists the I/O ports and the location of associated IC
sockets for installing either line drivers or I/O terminators.
(Refer to table 2 -1 items 10 and 11.) Port E8 is factory
equipped with Intel 8226 Bidirectional Bus Drivers and
requires no additional components. (Refer to paragraphs
2-22 and 2-23.)
2-12. RISE TIME/NOISE CAPACITORS
Eye pads are provided so that rise time/noise capacitors
may be installed as required on the individual serial I/O
pins. The selection of capacitor values is at the option of the
user and is normally a function of the particular environ-
ment. The location of these eye pads are as follows:
Capacitor Fig. 5-1
Fig. 5-2
C11 Z04 6Z04
C12 Z04 6Z83
C13
Z03 6ZC4
C14 Z04 6Z04
C16 Z03 6Z06
C17 Z03 6ZC6
C18 Z03 6Z06
iSBC 80/30
2-13.
JUMPER CONFIGURATION
The iSBC 80/30 includes a variety of jumper-selectable
options to allow the user to configure the board for his
parficular applicatio'n. Table 2-4 summarizes these
jumper-selectable options and lists the- grid reference
locations of the jumpers as shown in figure 5-1 (parts
location diagram) and figure 5-2 (schematic diagram).
Because the schematic consists of nine sheets, grid
references to figure 5-2 consists of four alphanumeric
characters. For example, grid reference 3ZB7 signifies
sheet 3 Zone B7.
Study table 2-5 carefully while making reference to
figures 5-1 and 5-2. If the default (factory configured)
jumper wiring is appropriate for a particular function, no
further actions is required for that function. If, however, a
different configuration is required, remove the default
jumper(s) and install an optional jumpers(s) as specified.
For most options, the information in table 2-4 is suffi-
cient for proper configuration. Additional information,
where necessary for clarity, is described in subsequent
paragraphs.
2-14. ROM/EPROM CONFIGURATION
Table 2-5 lists the jumper configurations and associated
address block for the various 'types of compatible Intel
ROM/EPROM chips.
2-15. ON-BOARD RAM ADDRESSES
This on-board RAM can be accessed by the on-board
8085A microprocessor (CPU) as well as by other bus
masters in the system via the
~1ultibus.
Addresses for on-
board 8085A access and for system access are assigned as
described in
paragraph~
2-16 and 2-17, respectively.
Table 2-3. Line Driver and 1/0 Terminator Locations
1/0 Driver/
Fig. 5·1 Fig. 5·2
Port
Bits
Terminator
Grid Grid
Ref.
Ref
E8 0-7
None Required
- -
8255A
E9
0-3 A5 Z06 4ZA3
PPI 4-7 A6 Z06 4ZA3
Interface
EA
0-3 A4 Z07 4ZC3
4-7 A3 Z07 4Z83
8041/8741
1
0-3 A7 Z06 5Z03
UPI
4-7 A8 Z06 5ZC3
Interface
0-3
(Optional)
2
A10
Z05 5Z83
4-7 A11 Z05
5Z83
-
TO, T1 A9 Z05 5ZC3
2-4