Troubleshooting Rx2660 Memory; Memory Dimm Load Order; Memory Subsystem Behaviors - HP Integrity rx2660 User's & Service Manual

Table 48 Processor Events That Could Light System Insight Display LEDs (continued)
Diagnostic Sample IPMI Events
LED(s)
Processors Type E0h, 67d:26d
BOOT_MONARCH_TIMEOUT
Processors Type E0h, 57d:26d
BOOT_INCOMPATIBLE_SLAVE
Processor Type E0h, 56d:26d
BOOT_INCOMPATIBLE_ PAL
Processors Type E0h, 34d:26d
BOOT_CPU_FAILED
Processors Type E0h, 33d:26d
BOOT_CPU_EARLY_TEST_FAIL
Processors Type 02h, 25h:71h:80h
MISSING_FRU_DEVICE

Troubleshooting rx2660 Memory

The memory controller logic in the zx2 chip supports the eight slots for rx2660 servers. It provides
two physical ranks that hold two or four DIMMs in memory cells 0 and 1.

Memory DIMM Load Order

For a minimally loaded server, two equal-size DIMMs must be installed in slots 0A and 0B in the
DIMM slots on the system board. The DIMM load order of pairs is as follows; slots 0A and 0B,
then slots 1A and 1B, then 2A and 2B, then 3A and 3B.

Memory Subsystem Behaviors

The zx2 chip in the rx2660 server provides increased reliability of DIMMs. For example, previous
low end servers with zx1 chips provided error detection and correction of all memory DIMM
single-bit errors and error detection of most multi-bit errors within a memory DIMM pair, or 4 bits
per rank (this feature is called chip sparing).
The zx2 chip doubles memory rank error correction from 4 bytes to 8 bytes of a 128 byte cache
line, during cache line misses initiated by processor cache controllers and by Direct Memory Access
(DMA) operations initiated by I/O devices. This feature is called double DRAM sparing, as 2 of
72 DRAMs in any DIMM pair can fail without any loss of server performance.
Corrective action, DIMM/memory expander replacement, is required when a threshold is reached
for multiple double-byte errors from one or more DIMMs in the same rank. And when any
uncorrectable memory error (more than 2 bytes) or when no pair of like DIMMs is loaded in rank
0 of side 0. All other causes of memory DIMM errors are corrected by zx2 and reported to the
Page Deallocation Table (PDT) / diagnostic LED panel.
126 Troubleshooting
Cause Source
The logical SFW
monarch CPU
(thread) has
timed out
A logical slave SFW
CPU (thread) is
incompatible
with logical
monarch CPU
CPU PAL SFW
incompatible
with processor
A processor SFW
failed
A logical CPU SFW
(thread) failed
early self test
No physical BMC
CPU cores
present
Notes
Possible
seating or
failed
processor