Omron CJ2 CPU UNIT SOFTWARE User Manual page 17

5-7 Index Registers ...................................................................................................................... 5-86
5-7-1
5-7-2
5-7-3
5-7-4
5-7-5
5-8 Specifying Address Offsets.................................................................................................. 5-95
5-8-1
5-8-2
5-9 Checking Programs............................................................................................................... 5-98
5-9-1
5-9-2
5-9-3
5-9-4
5-10 Precautions .......................................................................................................................... 5-105
5-10-1
5-10-2
Section 6 I/O Memory Areas
6-1 I/O Memory Areas .................................................................................................................... 6-2
6-1-1
6-1-2
6-1-3
6-2 I/O Area..................................................................................................................................... 6-8
6-2-1
6-2-2
6-3 Data Link Area ....................................................................................................................... 6-13
6-4 Synchronous Data Refresh Area.......................................................................................... 6-14
6-5 CPU Bus Unit Area ................................................................................................................ 6-15
6-6 Special I/O Unit Area ............................................................................................................. 6-16
6-7 Pulse I/O Area ........................................................................................................................ 6-17
6-8 Serial PLC Link Area ............................................................................................................. 6-18
6-9 DeviceNet Area ...................................................................................................................... 6-19
6-10 Work Area ............................................................................................................................... 6-20
6-11 Holding Area .......................................................................................................................... 6-21
6-12 Auxiliary Area ........................................................................................................................ 6-23
6-13 Temporary Relay Area........................................................................................................... 6-24
6-14 Data Memory Area ................................................................................................................. 6-25
6-15 Extended Data Memory Area................................................................................................ 6-28
6-16 Timer Areas............................................................................................................................ 6-32
6-17 Counter Areas........................................................................................................................ 6-34
6-18 Task Flags .............................................................................................................................. 6-35
6-19 Index Registers ...................................................................................................................... 6-36
6-20 Data Registers ....................................................................................................................... 6-41
6-21 Condition Flags ..................................................................................................................... 6-43
6-22 Clock Pulses .......................................................................................................................... 6-45
CJ2 CPU Unit Software User's Manual
What Are Index Registers?....................................................................................................... 5-86
Using Index Registers............................................................................................................... 5-86
Processing Related to Index Registers..................................................................................... 5-91
Monitoring Index Registers ....................................................................................................... 5-92
Sharing Index and Data Registers between Tasks ................................................................... 5-93
Overview................................................................................................................................... 5-95
Examples of Address Offset Application................................................................................... 5-97
Errors during CX-Programmer Input......................................................................................... 5-98
Program Checks with the CX-Programmer............................................................................... 5-98
Debugging with the Simulator................................................................................................... 5-99
Program Execution Check ...................................................................................................... 5-102
Condition Flags....................................................................................................................... 5-105
Special Program Sections ...................................................................................................... 5-110
I/O Memory Area Overview ........................................................................................................ 6-2
I/O Memory Area Structure......................................................................................................... 6-4
Holding I/O Memory Values........................................................................................................ 6-6
Input Bits..................................................................................................................................... 6-8
Output Bits ................................................................................................................................ 6-10
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