AMD Am186 CC User Manual page 67

Table 3-7 Signal Descriptions (Continued)
Multiplexed
1
Signal Name
Signal(s)
DEBUG SUPPORT
QS1–QS0
The following signals are also used by emulators: A19–A0, AD15–AD0, {ADEN}, ALE, ARDY, BHE, BSIZE8, CAS1–
CAS0, CLKOUT, {CLKSEL2}–{CLKSEL1}, HLDA, HOLD, LCS, MCS3–MCS0, NMI, {ONCE}, QS1–QS0, RAS1–
RAS0, RD, RES, RESOUT, S2–S0, S6, SRDY, UCS, {UCSX8}, WHB, WLB, WR. For more information, see
Chapter 4, "Emulator Support."
CHIP SELECTS
LCS [RAS0]
[MCS0] {UCSX8}
PIO4
MCS1 [CAS1]
MCS2 [CAS0]
[MCS3] [RAS1]
PIO5
System Overview
Type Description
Queue Status 1–0 values provide information to the system
concerning the interaction of the CPU and the instruction queue.
The pins have the following meanings:
— O
Lower Memory Chip Select indicates to the system that a
memory access is in progress to the lower memory block. The
base address and size of the lower memory block are
O
programmable up to 512 Kbyte. LCS can be configured for 8-bit
or 16-bit bus size. LCS is three-stated with a pullup resistor
during bus-hold or reset conditions.
Midrange Memory Chip Selects 0–3 indicate to the system
that a memory access is in progress to the corresponding region
of the midrange memory block. The base address and size of
the midrange memory block are programmable. The midrange
chip selects can be configured for 8-bit or 16-bit bus size. The
midrange chip selects are three-stated with pullup resistors
during bus-hold or reset conditions.
O
[MCS0] can be programmed as the chip select for the entire
middle chip select address range.
Unlike the UCS and LCS chip selects that operate relative to the
earlier timing of the nonmultiplexed A address bus, the MCS
outputs assert with the multiplexed AD address and data bus
timing.
Am186™CC/CH/CU Microcontrollers User's Manual
Queue Status Pins
QS1 QS0 Queue Operation
0 0 None
First opcode byte fetched from
0 1
queue
1 0 Queue was initialized
Subsequent byte fetched from
1 1
queue
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