Receive Fifo - AMD Am186 CC User Manual

When both the FIFO and a transmit have been enabled (with the TFEN and TMODE bits),
hardware immediately checks the Transmit FIFO Threshold Reached (TTHRSH) bit in the
status register. The transmit FIFO threshold value is set to half-empty (FIFO contains eight
bytes of data) and is not programmable. The High-Speed UART can be programmed to
generate a maskable interrupt when the transmit FIFO reaches the threshold value.
Software must clear the TTHRSH bit, but hardware can set it again immediately if the FIFO
contains less than eight entries.
FIFO underflow occurs when the transmit FIFO becomes completely empty. The High-
Speed UART can be programmed with the TEMT bit to generate an interrupt on FIFO
underflow.
13.5.3.2

Receive FIFO

The receive FIFO provides for up to 32 bytes of receive data along with status associated
for each byte, including special-character matching, framing and parity error flags, and the
value of the address bit, if applicable.
When both the receiver and the receive FIFO have been enabled, through the RMODE bit
for the receiver and the RFEN bit for the receive FIFO, the serial port hardware immediately
checks for a receive FIFO threshold reached condition. The receive FIFO threshold value
is not programmable and is set at half full or 16 bytes of data present in the FIFO. The High-
Speed UART can be programmed to generate a maskable interrupt when the receive FIFO
reaches the threshold value. Software must clear the RTHRSH bit, but hardware sets it
again immediately if the FIFO contains 17 or more entries.
As data moves to the top of the FIFO, the associated status is placed in the Serial Port
Status (HSPSTAT) register. Status bits are set by the hardware and must be cleared by
software. The serial port can be configured to generate an interrupt based on serial port
status. Each status bit is individually maskable. If an interrupting status condition is detected
in the serial port, DMA requests from the receiver are disabled. This allows the interrupt
service routine to read the data from the receiver (or to peek at the data through the
HSPRXDP register) and take appropriate action. Enabling extended reads allows the status
to be read in a word-wide read from the Serial Port Receive Data (HSPRXD) register. The
status data in the upper byte of an extended read reflects only the current frame. However,
the HSPSTAT register continues to be updated normally and set bits must be cleared by
software.
The IDLED bit in the HSPSTAT register indicates instances where the threshold is never
reached because less than 16 bytes of data were sent. The IDLED bit is set (and can be
used to generate an interrupt with the HSPIMSK register) when the receive data line has
been idle for 40 bit times and receive data is available. This bit must be cleared by software.
FIFO overflow occurs when the receive FIFO is completely full and another character is
received, resulting in the loss of data. In a FIFO overflow condition, the last location of the
FIFO is overwritten with the last byte received. The High-Speed UART can be programmed
to generate a maskable interrupt on FIFO overflow with the OERIM bit.
13.5.3.3 Using the FIFOs in Polled, Interrupt, or DMA Mode
The High-Speed UART FIFOs can be used in Polled, Interrupt, or DMA modes.
Interrupt and DMA modes are described in "Interrupt Sources" on page 13-19 and "Interface
to General-Purpose DMA Channels" on page 13-21. When in Polled mode, the High-Speed
UART behavior is similar to the non-FIFO mode.
In Polled mode, software reads the received data by reading the HSPRXD register. The
HSPSTAT register is updated with the status of the next frame after each read of the receive
13-12
Asynchronous Serial Ports (UARTs)
Am186™CC/CH/CU Microcontrollers User's Manual