AMD Am186 CC User Manual page 347

Table A-1 Am186CC/CH/CU Microcontrollers Register Summary (Continued)
DEFAULT DEFAULT
15
NAME OFFSET
LOCATION VALUE
Programmable I/O (PIO) Registers
PMODE
PIOMODE0 3C0h FFC0h 0000h
15
PIODIR0 3C2h FFC2h 1EFFh PDIR15
PIODATA0 3C4h FFC4h ????h PDATA15 PDATA14 PDATA13 PDATA12 PDATA11 PDATA10 PDATA9
PIOSET0 3C6h FFC6h 0000h PSET15
PIOCLR0 3C8h FFC8h 0000h PCLR15 PCLR14 PCLR13 PCLR12
PMODE
PIOMODE1 3CAh FFCAh 0000h
31
PIODIR1 3CCh FFCCh 9FFFh PDIR31
PIODATA1 3CEh FFCEh ????h PDATA31 PDATA30 PDATA29 PDATA28 PDATA27 PDATA26 PDATA25 PDATA24 PDATA23 PDATA22 PDATA21 PDATA20 PDATA19 PDATA18 PDATA17 PDATA16
PIOSET1 3D0h FFD0h 0000h PSET31
PIOCLR1 3D2h FFD2h 0000h PCLR31 PCLR30 PCLR29 PCLR28 PCLR27 PCLR26 PCLR25 PCLR24 PCLR23 PCLR22 PCLR21
PMODE
PIOMODE2 3D4h FFD4h 0000h
47
PIODIR2 3D6h FFD6h FFF1h PDIR47
PIODATA2 3D8h FFD8h ????h PDATA47 PDATA46 PDATA45 PDATA44 PDATA43 PDATA42 PDATA41 PDATA40 PDATA39 PDATA38 PDATA37 PDATA36 PDATA35 PDATA34 PDATA33 PDATA32
PIOSET2 3DAh FFDAh 0000h PSET47
PIOCLR2 3DCh FFDCh 0000h PCLR47 PCLR46 PCLR45 PCLR44 PCLR43 PCLR42 PCLR41 PCLR40 PCLR39 PCLR38 PCLR37
Reset Configuration Register
RESCON 3DEh FFDEh ????h RCD15
Watchdog Timer Register
WDTCON 3E0h FFE0h C180h
ENA
Miscellaneous Registers
SYSCON 3F0h FFF0h 0000h
PRL 3F4h FFF4h 4001h
RELOC 3FEh FFFEh 20FCh DUAL
DEFAULT DEFAULT
15
NAME OFFSET
LOCATION VALUE
! = See the register or bit description in the Am186™CC/CH/CU Microcontrollers Register Set Manual, order #21916, for controller-specific details.
14 13 12 11
PMODE PMODE PMODE PMODE
14 13 12 11
PDIR14 PDIR13 PDIR12 PDIR11
PSET14 PSET13 PSET12 PSET11
PCLR11
PMODE PMODE PMODE PMODE
30 29 28 27
PDIR30 PDIR29 PDIR28 PDIR27
PSET30 PSET29 PSET28 PSET27
PMODE PMODE PMODE PMODE
46 45 44 43
PDIR46 PDIR45 PDIR44 PDIR43
PSET46 PSET45 PSET44 PSET43
RCD14 RCD13 RCD12 RCD11
WRST RSTFLAG NMIFLAG
Res
DSDEN PWD DISMEM
Res M/IO
14 13 12 11
10 9 8 7
PMODE PMODE PMODE PMODE PMODE
10 9 8 7
PDIR10 PDIR9 PDIR8 PDIR7 PDIR6
PDATA8 PDATA7 PDATA6
PSET10 PSET9 PSET8 PSET7 PSET6
PCLR10 PCLR9 PCLR8 PCLR7 PCLR6
PMODE PMODE PMODE PMODE PMODE
26 25 24 23
PDIR26 PDIR25 PDIR24 PDIR23 PDIR22
PSET26 PSET25 PSET24 PSET23 PSET22
PMODE PMODE PMODE PMODE PMODE
42 41 40 39
PDIR42 PDIR41 PDIR40 PDIR39 PDIR38
PSET42 PSET41 PSET40 PSET39 PSET38
RCD10 RCD9 RCD8 RCD7 RCD6
Res EXRST
DISIO ITF4 ! EXSYNC !
PRL
R[19–10]
10 9 8 7
6 5 4 3 2
PMODE PMODE PMODE PMODE
6 5 4 3 2
PDIR5 PDIR4 PDIR3 PDIR2
PDATA5 PDATA4 PDATA3 PDATA2
PSET5 PSET4 PSET3 PSET2
PCLR5 PCLR4 PCLR3 PCLR2
PMODE PMODE PMODE PMODE
22 21 20 19 18
PDIR21 PDIR20 PDIR19 PDIR18
PSET21 PSET20 PSET19 PSET18
PCLR20 PCLR19 PCLR18 PCLR17 PCLR16
PMODE PMODE PMODE PMODE
38 37 36 35 34
PDIR37 PDIR36 PDIR35 PDIR34
PSET37 PSET36 PSET35 PSET34
PCLR36 PCLR35 PCLR34 PCLR33 PCLR32
RCD5 RCD4 RCD3 RCD2
ES
Res
DISCLK
6 5 4 3 2
1 0
PMODE PMODE
1 0
PDIR1 PDIR0
PDATA1 PDATA0
PSET1 PSET0
PCLR1 PCLR0
PMODE PMODE
17 16
PDIR17 PDIR16
PSET17 PSET16
PMODE PMODE
33 32
PDIR33 PDIR32
PSET33 PSET32
RCD1 RCD0
Res
Res
1 0