Table of Contents
Advertisement
A destination-synchronized transfer differs from a source-synchronized transfer in that the
four cycle delay allows the destination device to deassert its DRQ signal four clocks before
another request is latched. Without this delay, the destination device would not have time
to deassert its DRQ signal. Because of the four extra cycles, a destination-synchronized
DMA channel allows other bus masters to take the bus during the idle states.
8.5.6.6.6
Using Buffer Queues or Circular Buffers
Note: This discussion assumes the channel is using a memory buffer (i.e., that the source
or destination address is programmed to increment or decrement). If the address is
programmed to remain constant, no memory buffer is in use, and neither buffer queues nor
circular buffers are used. See "Incrementing or Decrementing Addresses" on page 8-15 for
more information.
The GDxCON1 register contains two fields that specify whether the source and/or
destination addresses for that DMA channel should wrap when the addresses reach a
programmed boundary. These fields are programmed independently; wrapping could be
enabled for one address and not for the other. When wrapping is disabled, the memory
buffer is treated as a linear array. This is typically called a buffer queue .
With a buffer queue, data is written/read to sequential byte or word addresses until a terminal
count is reached. The DMA should be programmed to terminate when the terminal count
is reached, or data may be written past the end of the buffer.
When wrapping is enabled, the memory buffer is treated as a circular buffer (sometimes
called a ring buffer ). In this case, data is written/read to sequential byte or word addresses
until the programmed buffer length is reached, at which point the address is reset to its
initial value; data is never written outside the programmed buffer space. Circular buffers
can be programmed to be 1, 2, 4, 8, 16, 32, or 64 Kbytes in length, and must be aligned to
an address which is a multiple of the programmed size.
The use of a circular buffer reduces the overhead required in programming the DMA channel
and may result in more efficient use of the transmitting or receiving device. However, in the
case where a circular buffer is being used to receive data, software must ensure that valid
received data is removed from the buffer before it is overwritten by the DMA controller on
the next pass. Conversely, for transmit circular buffers, software must write valid transmit
data into the buffer before that buffer address is read by the DMA controller.
To avoid overwriting data in a circular buffer, compare the source address with the buffer
address. For example, the address contained in a DMA channel's source address registers
is the address of the next byte of data to be transmitted. Data that is logically between this
address and the buffer address being written to by software (in a circular fashion) has not
yet been transmitted. If the source address registers contain the address xxxx0050 when
software is writing to address xxxx0150, then the addresses from xxxx0050 through
xxx0149 contain valid data for transmission. Addresses outside of this range, but within the
buffer, do not contain valid data. This may be data that has already been transmitted or
may be addresses that have never been written.
For string data or other data which is naturally represented as consecutive bytes or words
in memory, using circular buffers involves additional overhead because the data must be
moved between its storage location and the circular buffer. For these data types, a buffer
queue may be a more efficient solution.
8-20
DMA Controller
Am186™CC/CH/CU Microcontrollers User's Manual
Advertisement
Table of Contents
