AMD Am186 CC User Manual page 296

In the case where the S/G bit is 1, only the D-channel data is prevented from being
switched through the GCI bus (i.e., the C/I0 channel could request access to this already
established TIC bus and transmit its information). The TIC bus request remains
unaffected (for example, if the microcontroller has earned the right to the GCI TIC bus
it does not give up this bus and keeps BAC and the TIC address active while waiting for
GO). As soon as the S-interface D-channel is clear, signified by the S/G bit cleared (GO),
the controller commences with D-channel data transmission.
Note: When GCI TIC access is granted, BAC = 0, regardless of S/G. At this point, both
C/I0 and the HDLC controller have access to the GCI TIC bus (i.e., if C/I0 data needs to
be transmitted it does not have to arbitrate for the GCI TIC bus—TIC bus access has already
been established). To relinquish the GCI TIC bus after a C/I0 or D-channel transmission,
both the C/I0 request (a software request) and the HDLC controller request (a hardware
request) must be deasserted. The HDLC controller cannot transmit back-to-back frames.
Therefore, if C/I0 keeps the TIC bus open (the TIC bus established by the HDLC controller),
another HDLC transmission does not occur until after the C/I0 gives up the TIC bus and
BAC = 1 in two successive frames (i.e., the TIC bus cannot be accessed again for at least
one GCI frame—regardless of whether the HDLC controller request or the C/I0 request
established the TIC bus).
6. After the completed transmission of an HDLC frame, signified by the HDLC controller
deasserting the TIC bus controller's RTS, the HDLC controller is withdrawn from the TIC
bus (BAC is set back to 1 in the following frame if a software TIC bus request has not
been made for C/I0 communication), and the HDLC controller is prevented from
accessing the TIC bus again for one GCI frame (i.e., the controller was moved into a
lower priority as mentioned earlier). This also applies even if a new HDLC frame is to
be transmitted in immediate succession. This gives all connected devices an equal
chance to access the TIC bus.
7. If a collision occurs at any time during the transmission of a D-channel HDLC frame, the
Am186CC microcontroller immediately ceases transmission (collision is signified to the
HDLC controller by deasserting CTS while in frame), returns to the D-channel monitoring
state (i.e., waits for another request to send and start over), and sends 1s over the
D-channel.
17.5.7.5.2 C/I0 Arbitration (Software Control)
Software controls the GCI Bus Accessed (BAC) bit through the Bus Access Request (BAR)
bit of the GCITDx register following a procedure very similar to the D-channel arbitration
scheme described above. This bit provides access to the C/I0 channel when TIC bus
support is enabled. Software should set the BAR bit whenever the microcontroller has C/I0
data available to transmit.
1. When BAR = 1, the TIC bus controller arbitrates access to the C/I0 channel.
2. The GCI TIC bus controller checks if the BAC bit is set to 1. If not, access is not currently
allowed—transmission is postponed. Only when BAC = 1 does the GCI TIC bus controller
continue with this access procedure. Otherwise, it remains in this state.
3. When BAC = 1, the GCI TIC bus controller, in the same frame, transmits the TIC bus
address (TBA2–TBA0) on the open drain output. On the TIC bus, binary 0s overwrite
binary 1s. Thus, low TIC bus addresses have higher priority.
4. After transmitting a TIC bus address bit, the GCI TIC bus controller reads back the value
to check whether its own address bit has been overwritten by a controller with higher
priority. This procedure continues until all three address bits are sent and confirmed—
thus granting access to the GCI TIC bus. In the event a bit is overwritten by an external
controller with higher priority, the GCI TIC bus controller withdraws immediately from the
17-18
General Circuit Interface (GCI)
Am186™CC/CH/CU Microcontrollers User's Manual