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The value of the MMCS register is set to 7FDBh and the MPCS register is set to 8183h,
which defaults MCS3–MCS0 each to 2 Kbytes with a total MCS block size of 8 Kbytes
at a base address of 3Fh, with external ready, and three wait states. However, the MCS
chip selects are not enabled until software writes to both the MMCS and MPCS registers.
Data bus widths are set as follows:
– LCS is 16 bits wide.
– Non-UCS and non-LCS memory (MCS, PCS, and the remaining memory that does
not reside in one of the enabled, memory chip-select regions) accesses are 16 bits
wide.
– All I/O accesses are 16 bits wide.
UCS is the inverse of the state of the UCSX8 that was latched on exiting external reset.
If UCSX8 is 0, UCS is 8 bits wide; if UCSX8 is 1, UCS is 16 bits wide. In either case,
UCS defaults to non-DRAM.
5-12
Chip Selects
Am186™CC/CH/CU Microcontrollers User's Manual
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