AMD Am186 CC User Manual page 166

Microcontrollers Register Set Manual , order #21916. Even when the ring size is set
to 1, that entry is still interpreted as a descriptor, not as the memory buffer itself.
5. Point to the first buffer descriptor by clearing the SDxCBD register to 0.
Program the Interrupt Conditions
The interrupt conditions are typically configured only once.
1. Write the interrupt handler address to the vector table. See Chapter 7, "Interrupts."
2. To generate an interrupt after transmitting the last byte of the packet, set the TEPI bit in
the SDxCON register to 1.
3. To generate an interrupt after detecting an unavailable buffer during transmission, set
the TBUI bit in the SDxCON register to 1.
4. To generate an interrupt after transmitting the last byte of the current buffer, set the TTCI
bit in the SDxCON register to 1. (Note that the TTCE bit in Word 2 of the transmit buffer
descriptor ring must also be set to 1.)
5. Program the priority of this channel relative to other channels during simultaneous
transfers using the P bit in the SDxCON register (this is typically configured only once).
A 00b is a low priority; a 01b, medium; and a 10b, high.
Software clears the status bits in SDxSTAT after receiving an interrupt. Software can
use the SDxCBD register to monitor the transmit and receive buffers. Software can also
use the SDxCTAD register to determine the address in memory where the DMA transmit
process was interrupted.
Add Data Buffers to the Transmit Descriptor Ring
To place a data buffer in an entry in the transmit buffer descriptor ring:
1. Find the first buffer descriptor for which the OWN bit is clear (bit = 0). This must be done
in a circular manner relative to the current buffer descriptor index. In systems where the
TXS0 or RXS0 bits are set, thereby inhibiting clearing of the OWN bits, software must
determine when it is safe to modify a descriptor ring entry.
2. Program the data buffer address.
a. Program the LADR bits in Word 0 to the low-order 16 address bits of the data buffer
pointed to by the descriptor.
b. Program the HADR bits in Word 1 to the high-order eight address bits of the data
buffer pointed to by the descriptor. The highest four bits of the address must be set to
0000b. These address bits do not exist on the Am186CC/CH/CU microcontrollers'
20-bit address but are provided for LANCE compatibility.
3. Program the data buffer size by setting the BCNT bits in Word 2 to the length in bytes
of the data buffer pointed to by the descriptor.
4. Initialize the transmit buffer descriptor ring entries.
a. Set to 1 the TTCE bit in Word 2 to enable interrupt on terminal count; or clear to 0 to
disable terminal count interrupt. (Note that the TTCI bit in the SDxCON register must
also be set to 1.)
b. Set to 1 the STP bit in Word 1 to indicate that this is the first buffer of the packet, or
clear to 0 if the buffer contains a continuation of a packet from another buffer.
c. Set to 1 the ENP bit in Word 1 to indicate that this is the last buffer of the packet, or
clear to 0 if the packet does not fit in one buffer and is continued in another.
8-32
DMA Controller
Am186™CC/CH/CU Microcontrollers User's Manual