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11.3
SYSTEM DESIGN
Table 11-1 lists the watchdog timer signals that are multiplexed with other microcontroller
functions. Pinstraps are sampled only at external reset and do not affect the pin's other
functions, so they are not shown in this table. Other multiplexed signals, when enabled,
either disable or alter any other functions that use the same pin.
.
Table 11-1
Watchdog Timer Multiplexed Signals
Signal
RES
NMI
Systems that require a guaranteed recovery time from software or hardware errors should
use the watchdog timer.
Generation of the internal NMI signal on the first watchdog timer time-out can be useful in
systems where it may be possible to recover from glitches, corrupted data, or incorrect code
without resetting either the controller or the board. This is especially true where potential
data recovery is important. Such systems should have the NMI interrupt handler routine in
ROM to ensure that it has not been corrupted by runaway code. However, in most systems,
the interrupt table, which must be located at address 00000h, is located in RAM and so is
subject to corruption.
Generation of the RESOUT signal should be used in systems where a system hang may
be caused by incorrect behavior of an external device. The watchdog timer reset duration,
and therefore the duration of the RESOUT signal on a watchdog timer reset, is 2
clocks. This allows sufficient time for external devices to reach their reset state.
The watchdog timer must function in all cases where either the software or external devices
have failed to respond appropriately. The watchdog timer has incorporated several features
to ensure that this is the case.
The watchdog timer is active after reset.
The watchdog timer's default configuration after a power-on reset is to generate a reset
on the first time-out and to assert the RESOUT signal.
Software can disable the Watchdog Timer Control (WDTCON) register after reset and,
while it is disabled, it can be written any number of times. When software enables the
watchdog timer, the register becomes read-only except for two flag bits. This allows
bootup or monitor code to disable the watchdog timer until the system has been
configured.
Each single write to the watchdog timer must be preceded by writes of a keyed sequence.
Detection of the keyed sequence allows a single write to the WDTCON register.
The watchdog timer time-out counter can only be reset by the initial enabling write to
the WDTCON register or by writing a special key sequence to the WDTCON register.
These features guarantee that the watchdog timer is not affected by runaway code.
Software can determine whether an NMI or reset event was caused by an external source
or by the watchdog timer by reading the WDTCON register. The NMIFLAG bit is set when
the watchdog timer generates an NMI; the RSTFLAG bit is set when the watchdog timer
generates a reset. Software can clear, but not set, these bits.
11-2
Watchdog Timer
Function
Controller reset
Nonmaskable interrupt
Am186™CC/CH/CU Microcontrollers User's Manual
Multiplexed
Default
Signal(s)
Signal
—
RES
—
NMI
16
processor
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