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In addition, the USB peripheral controller supports the following:
An unlimited number of device descriptors.
A total of six endpoints: one control endpoint; one interrupt endpoint; and four data
endpoints that can be configured as control, interrupt, bulk, or isochronous. The interrupt,
bulk, and isochronous endpoints can be configured for the IN or OUT direction.
Two of the data endpoints have 16-byte FIFOs and two have 64-byte FIFOs.
Fully integrated differential driver, which directly supports the USB interface.
Specialized hardware, which supports adaptive isochronous data streams and
automatically synchronizes with HDLC data streams.
General-purpose DMA and SmartDMA channels.
1.4.2.2
HDLC Channels (Chapter 15) and TSAs (Chapter 16)
The Am186CC microcontroller provides four HDLC channels and the Am186CH HDLC
CC
CH
microcontroller provides two HDLC channels. These channels support the HDLC, SDLC,
LAP-B, LAP-D, PPP, and V.120 protocols. The HDLC channels can also be used in
transparent mode to support V.110. Each HDLC channel can connect to an external serial
interface directly (non-multiplexed mode), or can pass through a TSA (multiplexed mode).
The flexible interface multiplexing arrangement allows each HDLC channel to have its own
external interface, to share a common PCM highway or other time division multiplexed
(TDM) bus with the other channels, or to work in some combination.
The Am186CC microcontroller supports raw DCE, PCM highway, and GCI interfaces.
CC
The Am186CH HDLC microcontroller supports raw DCE and PCM highway interfaces.
CH
Each HDLC channel's independent TSA allows it to extract a subset of data from a TDM
bus. It can isolate the entire frame or as little as one bit per frame. The channel's 12-bit
counter defines the start/stop bit times as the number of bits after frame synchronization.
The time slot can be an arbitrary number of bits up to 4096 bits. Start bit and stop bit times
identify the isolated portion of the TDM frame. Support of less than eight bits per time slot,
or bit slotting , allows isolation of from one to eight bits in a single time slot, providing a
convenient way to work with D-channel data. Each TDM bus can have up to 512 8-bit time
slots. Support of these features allows interoperation with PCM highway, E1, IOM-2, T1,
and other TDM buses.
To make the Am186CC and Am186CH microcontrollers attractive devices for use where
general HDLC capability is required, the HDLC channels support the following features:
Clear-to-Send (CTS) and Ready-to-Receive (RTR) hardware handshaking and auto-
enable operation
Collision detection for multidrop applications
Transparency mode
Address comparison on receive
Flag or mark idle operation
Two dedicated buffer descriptor ring SmartDMA channels per HDLC channel
Transmit and receive FIFOs
Full-duplex data transfer
Architectural Overview
Am186™CC/CH/CU Microcontrollers User's Manual
1-7
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