AMD Am186 CH Manuals

Manuals and User Guides for AMD Am186 CH. We have 1 AMD Am186 CH manual available for free PDF download: User Manual

AMD Am186 CH User Manual (376 pages)

Brand: AMD | Category: Microcontrollers | Size: 5.95 MB

Table of Contents
5
Preface

19
- Introduction
  
  19
  - Comm86 Family
    19
  - Purpose of this Manual
    19
    
    Intended Audience
    19
    
    Overview of this Manual
    19
  - Related Documents
    21
    
    AMD Documentation
    21
    
    Additional Information
    22
  - Documentation Conventions
    22
  - Table 0-1 Documentation Conventions
    22
  - Microcontroller-Specific Information
    23
Chapter 1 Architectural Overview

25
- Features
  25
- Am186Cc Communications Controller
  25
CHAPTER 2 CONFIGURATION BASICS 2.1 Overview

41
CHAPTER 3 SYSTEM OVERVIEW 3.1 Overview

51
- Table 3-2 Multiplexed Signal Trade-Offs Ordered by PIO
  53
System Overview

51
- Overview
  51
- System Design
  51
- Table 3-1 Multiplexed Signal Trade-Offs
  51
Chapter 4 Emulator Support

87
- Overview
  87
- System Design
  87
  - Multiplexed Pins
    87
  - Emulator Connection
    87
- Operation
  88
  - Usage
    88
  - Emulator-Related Signals
    88
    
    A19-A0
    88
    
    Ad15-Ad0
    88
    
    Aden} / Bhe
    88
    
    Ale
    89
    
    ARDY and SRDY
    89
    
    Bhe
    89
    
    Bsize8
    89
    
    CAS1-CAS0] and [RAS1-RAS0]
    89
    
    Clkout
    89
    
    Lcs
    89
    
    Mcs3-Mcs0
    90
    
    Once
    90
    
    Qs1-Qs0
    90
    
    Ras1-Ras0]
    90
    
    Res
    90
    
    Resout
    90
    
    Hardware-Related Considerations
    91
    
    S2-S0
    91
    
    Srdy
    91
    
    Ucs
    91
    
    UCSX8} and WLB
    91
    
    WHB and WR
    91
    
    Wlb
    91
  - Comparison to Other Devices
    91
- Initialization
  91
Chapter 5 Chip Selects

93
- Overview
  93
- Block Diagram
  94
- System Design
  94
- Figure 5-1 Chip Selects and DRAM Block Diagram
  94
- Registers
  95
- Table 5-1 Chip Selects Multiplexed Signals
  95
- Table 5-2 Chip Select Register Summary
  95
- Operation
  96
  - Usage
    96
  - Selecting Memory and I/O Space
    97
    
    Lcs
    97
    
    Mcs3-Mcs0
    97
    
    Ucs
    97
    
    Pcs7-Pcs0
    98
  - Selecting DRAM Using the Chip Selects
    99
  - Figure 5-3 Chip Selectable I/O Space
    99
  - Table 5-3 Signal Function When UCS or LCS Is Configured for DRAM
    99
  - Overlapping Chip Selects
    100
  - Configuring Address and Data Buses
    101
    
    Non-UCS and Non-LCS
    101
    
    PCS I/O Space
    101
    
    UCS and LCS
    101
  - Programming Ready Signals and Wait States
    102
  - Chip Select Timing
    102
  - Hardware-Related Considerations
    102
  - Software-Related Considerations
    102
  - Comparison to Other Devices
    103
- Initialization
  103
Chapter 6 Dram Controller

105
- Overview
  105
- Block Diagram
  106
- System Design
  106
- Figure 6-1 Chip Selects and DRAM Block Diagram (same as Figure 5-1)
  106
- Table 6-1 DRAM Multiplexed Signals
  106
- Registers
  107
- Operation
  107
  - Usage
    107
  - DRAM Supported
    107
  - Table 6-2 DRAM Controller Register Summary
    107
  - DRAM Interface
    108
  - Table 6-3 DRAM Supported by the Am186Cc/Ch/Cu Microcontrollers
    108
  - Table 6-4 Address Multiplexing Reference
    108
  - Option to Overlap DRAM with PCS
    109
  - DRAM Refresh
    109
    
    DRAM Refresh Cycle
    109
    
    DRAM Refresh Intervals
    110
  - Hardware-Related Considerations
    110
  - Software-Related Considerations
    110
  - Table 6-5 Refresh Interval Times
    110
  - Comparison to Other Devices
    111
- Initialization
  111
Chapter 7 Interrupts

113
- Overview
  113
- Block Diagram
  114
- System Design
  115
- Figure 7-1 Interrupts Block Diagram
  115
- Table 7-1 Interrupt Multiplexed Signals
  116
- Registers
  116
- Registers
  117
- Table 7-2 Interrupt Controller Register Summary
  117
- Operation
  118
  - Usage
    118
    
    Types of Interrupt Channels
    118
    
    Using Maskable Interrupts
    119
    
    Using Nonmaskable Interrupts
    120
  - Definitions of Interrupt Terms
    120
  - Interrupt Sequence
    121
    
    Figure 7-2 Interrupt Vector Translation
    121
    
    Requesting the Interrupt
    121
    
    Acknowledging the Interrupt
    122
    
    End-Of-Interrupt (EOI)
    122
    
    Returning from the Interrupt
    122
    
    Servicing the Interrupt
    122
  - Interrupt Priority
    123
    
    Maskable Hardware Interrupt Priority
    123
    
    Nonmaskable Interrupt and Software Interrupt Priority
    123
    
    Table 7-3 Interrupt Types
    124
  - Maskable Interrupts
    125
    
    Maskable Interrupt Cycle
    125
    
    Considerations for NMI, Software Interrupts, and Traps
    126
    
    Interrupts in Polled Mode
    126
    
    Maskable Interrupt Overview
    126
    
    Figure 7-3 Partial Block Diagram of Interrupt Controller Scheme
    127
    
    Maskable Interrupt Block Diagram
    127
    
    Table 7-4 Interrupt Channel Map
    128
    
    Table 7-5 Interrupt Channel Sources
    129
    
    Pios as Interrupts
    130
    
    Registers Used
    130
  - Nonmaskable Interrupts
    130
    
    Breakpoint Interrupt (Interrupt Type 03H)
    131
    
    Divide Error Exception (Interrupt Type 00H)
    131
    
    INT0 Detected Overflow Exception (Interrupt Type 04H)
    131
    
    Nonmaskable Interrupt (Interrupt Type 02H)
    131
    
    Software Interrupts
    131
    
    Trace Interrupt (Interrupt Type 01H)
    131
    
    Array Bounds Exception (Interrupt Type 05H)
    132
    
    ESC Opcode Exception (Interrupt Type 07H)
    132
    
    Unused Opcode Exception (Interrupt Type 06H)
    132
  - Software-Related Considerations
    132
  - Comparison to Other Devices
    132
- Initialization
  132
Chapter 8 Dma Controller

135
CHAPTER 9 PROGRAMMABLE I/O SIGNALS 9.1 Overview

179
- Figure 9-1 PIO Operation Block Diagram
  180
  - System Design
    180
    
    Table 9-1 PIO Multiplexed Signals
    181
    
    Defining the PIO Signal as Input or Output
    183
    
    Registers
    183
    
    Table 9-2 PIO Register Summary
    183
    
    Usage
    183
    
    Driving Data on the PIO
    184
    
    Setting and Clearing Data
    184
    
    Table 9-3 PIO Mode and PIO Direction Register Bit Settings
    184
    
    Table 9-4 PIO Set and PIO Clear Registers' Effect on PIO Data Register
    184
    
    Using Pios as Open-Drain Outputs
    184
    
    Comparison to Other Devices
    185
    
    Hardware-Related Considerations
    185
    
    Software-Related Considerations
    185
    
    Figure 10-1 Programmable Timers Block Diagram
    187
  - Overview
    187
    
    System Design
    188
    
    Table 10-1 Programmable Timer Multiplexed Signals
    188
    
    Table 10-2 Programmable Timers Register Summary
    188
    
    Operation
    189
  - Table 10-3 Timer 0 and Timer 1 Behavior
    190
Chapter 10 Programmable Timers

191
- Requesting Interrupts
  191
- Figure 10-2 Pulse Width Demodulation Example
  192
- Software Polling
  192
- CHAPTER 11 Figure 11-1 Watchdog Timer Block Diagram
  
  195
- Overview
  195
- System Design
  196
- Table 11-1 Watchdog Timer Multiplexed Signals
  196
- Figure 11-2 Access to the WDTCON Register
  197
- Registers
  197
- Table 11-2 Watchdog Timer Register Summary
  197
- Overview
  198
- Software-Related Considerations
  199
Chapter 12 Serial Communications Overview

201
- Table 12-1 Multiplexed Signal Trade-Offs for Serial Interfaces
  202
  - System Design
    202
  - Controller
    203
  - Figure 12-1 HDLC Control Application
    204
  - Figure 12-2 POTS Linecard
    204
  - Figure 12-3 ISDN Application
    205
  - Figure 12-4 ISDN Application with GCI-To-PCM Highway Conversion
    205
  - Serial Communications Introduction
    206
    
    Fifos
    207
    
    Figure 12-5 CTS/RTR Protocol
    207
    
    Simplex, Half-Duplex, and Full-Duplex Systems
    208
Chapter 13 Asynchronous Serial Ports (Uarts)

209
- Figure 13-1 Uarts Block Diagram
  210
  - System Design
    211
  - Table 13-1 Uarts Multiplexed Signals
    211
  - Operation
    212
  - Transmit
    213
  - Receive
    214
  - Autobaud Mode (High-Speed UART Only)
    215
  - Figure 13-2 Uarts Frame
    216
  - Figure 13-3 Uarts Timing
    216
- Data
  216
  - Address Bits
    217
  - Receive Status and Data
    218
  - Fifos (High-Speed UART Only)
    219
    
    Receive FIFO
    220
    
    CTS/RTR Hardware Flow Control
    221
    
    Clock Sources and Baud Rate
    222
    
    Figure 13-4 RTR_U Signal Behavior
    222
    
    Figure 13-5 RTR_HU Signal Behavior with Receive Fifos
    222
    
    Figure 13-6 Uarts Clock
    223
    
    Programming the Baud Rate
    223
    
    Table 13-3 Baud Rate Table for Uarts
    223
    
    Receiver Bit Sampling
    224
    
    Figure 13-7 Worst Case % Error Per Bit Vs. Baud Divisor Without Autobaud Enhancement
    225
    
    Figure 13-8 Detectable Baud Ranges for Various Frequencies
    225
    
    Figure 13-9 Autobaud Enhancement
    226
    
    Table 13-4 Examples of Autobaud Enhancement
    226
    
    Interrupt Sources
    227
    
    Break Detection and Generation
    228
    
    Figure 13-10 Break Character Example
    228
    
    Interface to General-Purpose DMA Channels
    229
    
    Comparison to Other Devices
    231
Chapter 14 Synchronous Serial Port (Ssi)

233
- Figure 14-1 SSI Block Diagram
  234
- System Design
  234
Chapter 15 High-Level Data Link Control (Hdlc)

243
- Block Diagram
  244
- System Design
  246
- Registers
  247
- Table 15-2 HDLC Register Summary
  248
- Operation
  249
- Interface
  250
- General HDLC Options
  251
- HDLC Transmitter
  252
  - HDLC Receiver
    256
    
    Figure 15-7 HDLC Receiver Block Diagram
    257
    
    HDLC and Smartdma
    260
- HDLC Receiver
  261
  - Interrupts
    262
  - Software-Related Considerations
    263
Chapter 16 Hdlc External Serial Interface Configuration (Tsas)

265
- Block Diagrams
  267
- System Design
  269
Chapter 17 General Circuit Interface (Gci)

279
- System Design
  281
- Registers
  283
- Transmitting Data
  284
- Receiving Data
  285
- GCI Structure: Channels and Frames
  286
- GCI Bus
  287
  - Figure 17-4 Bus Activation/Deactivation
    288
  - GCI Bus Reversal
    289
  - Figure 17-5 Downstream Versus Upstream
    290
  - GCI Interface Signals
    291
    
    GCI-To-PCM Converted Pin Interface
    292
    
    C/I Channel Operation
    293
    
    TIC Bus Support
    294
    
    IC Channel Operation
    297
    
    Software-Related Considerations
    298
Chapter 18 Universal Serial Bus (Usb)

299
- Block Diagram
  300
- USB Transceiver Interface
  301
- Figure 18-2 USB with Internal Transceiver
  302
- USB Clock Source
  303
- Isochronous Synchronization Signals
  304
  - Registers
    305
  - Operation
    308
- Programming the Control Endpoint
  309
- Programming Data Endpoints
  310
- Data Transmission and Data Types
  314
  - USB Reset
    315
  - Handling USB Data
    316
  - Interrupt-Driven I/O
    317
    
    DMA/FIFO Interaction
    318
    
    Setting up DMA for USB
    319
    
    Error Recovery on Bulk and Interrupt Endpoints
    320
  - Isochronous Transfer Synchronization
    321
  - Isochronous Transfer Features
    322
  - Command Handling
    324
    
    Controller Hardware
    325
  - Command Protocol
    326
    
    Data Transfer Using the Control Endpoint
    327
    
    Data Transfer with the Interrupt Endpoint
    328
- Interrupt Endpoint Definition
  329

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Video Card Computer Hardware Motherboard Microcontrollers Software

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AMD Am186 CH Manuals

AMD Am186 CH User Manual (376 pages)

Table of Contents

Preface

Introduction

Chapter 1 Architectural Overview

CHAPTER 2 CONFIGURATION BASICS 2.1 Overview

CHAPTER 3 SYSTEM OVERVIEW 3.1 Overview

System Overview

Chapter 4 Emulator Support

Chapter 5 Chip Selects

Chapter 6 Dram Controller

Chapter 7 Interrupts

Chapter 8 Dma Controller

CHAPTER 9 PROGRAMMABLE I/O SIGNALS 9.1 Overview

Chapter 10 Programmable Timers

CHAPTER 11 Figure 11-1 Watchdog Timer Block Diagram

Chapter 12 Serial Communications Overview

Chapter 13 Asynchronous Serial Ports (Uarts)

Chapter 14 Synchronous Serial Port (Ssi)

Chapter 15 High-Level Data Link Control (Hdlc)

Chapter 16 Hdlc External Serial Interface Configuration (Tsas)

Chapter 17 General Circuit Interface (Gci)

Chapter 18 Universal Serial Bus (Usb)

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AMD Categories