AMD Am186 CC User Manual page 273

HDLC External Serial Interface Configuration (TSAs)
Figure 16-5 on page 16-10 demonstrates the muxing logic for an ISDN basic-rate GCI
interface. The muxes at each stage level have been removed for clarity. In their place is the
end data path established after proper mux initialization. This figure illustrates the following:
1. Adjustable time slot size: eight bits for each GCI B channel and two bits for the GCI D
channel
2. Isolation of single time slots 0, 1, and 3
3. GCI B and D channel isolation
4. GCI support
5. Multiplexed mode for interface A (where multiple HDLC channels are multiplexed onto
one line)
Depending on whether you are transmitting or receiving, Figure 16-5 on page 16-10 can
be read: Stage 1, Stage 2, Stage 3; or Stage 3, Stage 2, Stage 1.
In Stage 1, the GCI controller extracts the GCI Monitor (Mon), Command/Indicate (C/I),
Intercommunication (IC), and Terminal Interchip Communication (TIC) channels. At the end
of stage 1, the HDLC data is multiplexed with the GCI channel data (the B1-, B2- and D-
channel ISDN data is present as well as the GCI Mon, C/I, IC, and TIC data).
In Stage 2, all channels are logically muxed onto one internal bus heading to and from
interface A. The GCI B and D channels are isolated.
In Stage 3, each HDLC clock is only active during the time slot for the channel it is to transmit
or receive. TSA A is configured to enable HDLC clocks for GCI channel D data. TSA B is
configured to enable clocks for GCI B2 channel data. TSA C is configured to enable clocks
for GCI B1 channel data.
Am186™CC/CH/CU Microcontrollers User's Manual 16-9