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pin
Refers to a physical wire on a chip which is available
externally. Compare to signal.
pinstrap
A pinstrap is used to enable or disable features based
on the state of the pin during an external reset. The pin-
strap must be held in its desired state for at least
4.5 clock cycles after the deassertion of the RES signal.
Note that the pinstraps are sampled in an external reset
only (when the RES signal is asserted) not during an
internal watchdog-timer generated reset.
PIO
Programmable input/output. Physical pins on the
Am186CC communications controller that can be used
for any purpose the system designer requires. The sig-
nal on a PIO pin can be sampled through a register and
can be driven High or Low by setting or clearing the
associated bit in the appropriate register.
pipe
A logical abstraction representing the association
between an endpoint on a USB device and software on
the host. A pipe has several attributes; for example, a
pipe may transfer data as streams (stream pipe) or mes-
sages (message pipe).
polled mode
One of three modes supported by the Am186CC com-
munications controller for serial communications. In
polled mode, software reads a status register in a loop,
and reads received data or transmits data depending on
the status register indicator bits. Compare to interrupt
mode and DMA mode.
port
Point of access to or from a system or circuit. For USB,
the point where a USB device is attached.
POTS
Plain old telephone service.
power-on reset
See external reset.
PPP
Point to point protocol.
PRI
Primary rate interface.
programmable priority
Each interrupt channel has eight levels of programma-
ble priority that are set in the channel's control register.
Programmable priority determines which interrupt to
service when two interrupts are requested at the same
time. An interrupt service routine is interrupted by
another interrupt request of equal or higher programma-
ble priority, as long as the Interrupt-enable Flag (IF) in
the Processor Status Flags (FLAGS) register is set. For
Glossary
Am186™CC/CH/CU Microcontrollers User's Manual
more information about setting the FLAGS register, see
the Am186™CC/CH/CU Microcontrollers Register Set
Manual , order #21916. If the programmable priority lev-
els are equal, the overall priority number is used.
PWD
Pulse width demodulation.
raw DCE
One of the external interfaces supported by the
Am186CC communications controller HDLC channels.
Raw DCE is a synchronous serial bus generally used in
modem and other high-speed serial applications. Raw
DCE runs at up to 10 Mbit/s. The Am186CC communi-
cations controller implementation requires transmit
(TCLK) and receive (RCLK) clock inputs, and has
receive data (RXD), transmit data (TXD), and the Clear-
To-Send (CTS) and Ready-To-Receive (RTR) flow con-
trol signals.
receiver
The portion of logic for an HDLC channel, SmartDMA
channel, or UART that processes information coming
into the Am186CC communications controller.
reset
See external reset , internal reset , and system reset.
ring buffer
See circular buffer.
router
The part of a communications network that receives
transmissions and forwards them to their destinations
using the shortest route available. Data may travel
through multiple routers on the way to their destination.
RTR
Ready-to-receive. See CTS/RTR.
RTS
Ready-to-send.
SCIT
Special circuit interface for terminals.
SDLC
Synchronous data link control. A data transmission pro-
tocol used by networks using Systems Network
Architecture (a communications format, advanced by
IBM, used on local-area networks to allow multiple sys-
tems access to centralized data). SDLC defines the
format used to transmit the data traveling over network
lines.
R
S
Glossary-7
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