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back to the beginning of the buffer and continues writing
or reading data. Sometimes called a ring buffer. Com-
pare to buffer queue.
CO
Central office.
codec
Coder-decoder. Also referred to as a compressor-
decompressor. Any technology used to encode (or com-
press) and decode (or decompress) data, which can be
done with hardware, software, or any combination of the
two. Typically used for digital audio or video data
streams.
control endpoint
A USB endpoint used to transfer USB commands and
device configuration data between the host and device.
The control endpoint is common to, and is required by,
all USB device class specifications. The control end-
point features are not programmable. Compare to
interrupt endpoint and data endpoint .
CPU
Central processing unit. The control unit or micropro-
cessor of a computer system.
CRC
Cyclic redundancy check. A check performed on data to
see if an error has occurred in transmitting, reading, or
writing the data. The result of a CRC is typically stored
or transmitted with the checked data. The stored or
transmitted result is compared to a CRC value calcu-
lated for the data to determine if an error has occurred.
CTR
Clear to receive.
CTS/RTR
Clear-to-send/ready-to-receive. A symmetrical interface
between two serial ports that provides hardware flow
control when both ports are sending and receiving data.
The CTS signal of each port is connected to the RTR
signal of the other port. When the transmitter sends a
CTS signal and the receiver sends a RTR signal, data
can be transferred from the transmitter to the receiver
between the ports.
data endpoint
A USB endpoint used to transfer data from the host to
the device, or vice versa. Each data endpoint is individ-
ually programmable as to direction (IN or OUT relative
to the host), transfer type (bulk, isochronous, or inter-
rupt), and maximum packet size. Compare to control
endpoint and interrupt endpoint .
Glossary-2
D
Am186™CC/CH/CU Microcontrollers User's Manual
Glossary
data transparency
A data stream that happens to contain a data sequence
that is the same as a flag, mark, or abort sequence is
disguised during transmission so it is not misconstrued
as an actual flag, mark, or abort. See also bit stuffing
and bit unstuffing.
DCE
Data communications equipment. Any device that con-
nects a computer to a network, such as a modem. See
also raw DCE.
default address
An address defined by the USB specification and used
by a USB device when it is first powered on or reset. The
default address is 00h.
descriptor ring
A block of memory that the CPU and software use to
control and describe data buffers.
destination-synchronized transfer
See synchronized transfer.
device
See USB device.
device address
The address of a device on the USB. The device
address is the default address when the USB device is
first powered on or reset. Hubs and functions are
assigned a unique device address by USB software.
DMA
Direct memory access. A means of transferring data
from a source (a device or block of memory) directly to
a destination (also a device or block of memory) without
passing the information through the processor. See also
general-purpose DMA and SmartDMA channel .
DMA latency
The time period between the DMA request generation
and the actual running of the bus cycles associated with
the DMA transfer. See also latency, interrupt latency,
and HOLD latency.
DMA mode
One of three modes supported by the Am186CC/CH/
CU microcontrollers for serial communications. In DMA
mode, software programs the DMA transfer registers,
then the DMA hardware performs the entire transfer
with no software intervention except for error-handling.
Compare to polled mode and interrupt mode .
DMA transfer
A unit of work involving the transferring of data into or
out of memory using DMA capabilities.
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