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data in memory so that the association of status and data is not lost. This behavior is not
affected by enabling or disabling the receive FIFO on the High-Speed UART.
Unlike the other status interrupts that move through the receive FIFO with their associated
data, the OERIM bit provides immediate notification of an overrun error condition. Software
can determine where the overrun occurred since the OER status bit travels through the
FIFO with the associated data. The OERIM error bypasses the FIFO and does an immediate
interrupt.
When extended writes are enabled, the value of the address bit is written to the high byte
of the (H)SPTXD register. When extended writes are not enabled, the value of the address
bit is taken from the value of the transmit Address Bit (AB) field in the serial port control
register at the time that the data is written to the transmit holding register. This bit is cleared
after each transfer of the data out of the holding register into either the transmit shift register
or the High-Speed UART FIFO.
When extended reads are enabled, the value of the address bit is read from the high byte
of the (H)SPRXD register, and also sets the AB bit in the status register. When extended
reads are not enabled, the value of the received address bit is placed in the received Address
Bit (AB) field of the (H)SPSTAT status register and must be cleared by software. This means
that applications needing to send or receive a string of characters with the address bit
cleared can use DMA to transfer the data to or from the serial port. Applications that require
the address bit set, or a mixture of the bit set and cleared, may use the DMA but must take
an interrupt each time the address bit is set. This is true regardless of the use of the FIFO.
For information about the use of the CTS/RTR protocol with DMA, see "CTS/RTR Hardware
Flow Control" on page 13-13.
For more information about using the UARTs and DMA, see Chapter 8, "DMA Controller."
13.5.10
Hardware-Related Considerations
The signals for the UART and flow-control for the High-Speed UART are multiplexed with
HDLC Channel D. For more information, see Table 13-1 on page 13-3.
13.5.11
Software-Related Considerations
Always program the configuration registers before setting the TMODE or RMODE bit to 1.
The most efficient data transfer operation (least software intervention, highest average
data transfer rate, and least opportunity for FIFO overrun) is when using FIFOs, DMA,
and CTS/RTR flow control.
In a multidrop system, hardware flow control must be enabled for only a single pair of
devices at any one time.
Always flush FIFOs before new data transfers.
The UARTs are multiplexed with HDLC. The Interface 4 Select (ITF4) bits in the System
Configuration (SYSCON) register must be configured for the UART interface.
13-22
Asynchronous Serial Ports (UARTs)
Am186™CC/CH/CU Microcontrollers User's Manual
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