AMD Am186 CC User Manual page 61

Table 3-7 Signal Descriptions (Continued)
Multiplexed
1
Signal Name
Signal(s)
[PIO34]
BHE
{ADEN}
BSIZE8
[DS]
DEN
[PIO30]
[DRQ0] PIO9
DRQ1
System Overview
Type Description
Bus High Enable: During a memory access, BHE and the least-
significant address bit (AD0) indicate to the system which bytes
of the data bus (upper, lower, or both) participate in a bus cycle.
The BHE and AD0 pins are encoded as follows:
BHE is asserted during t
O
t . BHE does not require latching. BHE is three-stated with a
W
pullup during bus-hold and reset conditions.
WLB and WHB implement the functionality of BHE and AD0 for
high and low byte write enables, and they have timing
appropriate for use with the nonmultiplexed bus interface.
BHE also signals DRAM refresh cycles when using the
multiplexed address and data (AD) bus. A refresh cycle is
indicated when both BHE and AD0 are High. During refresh
cycles, the AD bus is driven during the t
during the t
is undefined during a refresh cycle. For this reason, the A0 signal
cannot be used in place of the AD0 signal to determine refresh
cycles.
Bus Size 8 is asserted during t
— O
is deasserted to indicate a 16-bit cycle.
Data Enable supplies an output enable to an external data-bus
transceiver. DEN is asserted during memory and I/O cycles.
O
DEN is deasserted when DT/R changes state. DEN is three-
stated with a pullup during bus-hold or reset conditions.
DMA Requests 0 and 1 indicate to the microcontroller that an
STI
external device is ready for a DMA channel to perform a transfer.
DRQ1–[DRQ0] are level-triggered and internally synchronized.
DRQ1–[DRQ0] are not latched and must remain active until
— STI
serviced.
Am186™CC/CH/CU Microcontrollers User's Manual
Data Byte Encoding
BHE AD0
0 0
0 1
1 0
1 1
and remains asserted through t
1
, t , and t phases. The value driven on the A bus
2 3 4
Type of Bus Cycle
Word transfer
High byte transfer (bits
15–8)
Low byte transfer (bits
7–0)
Refresh
phase and three-stated
1
–t to indicate an 8-bit cycle, or
1 4
and
3
3-11