AMD Am186 CC User Manual page 365

initialization, 17-20
interface signals, 17-13
interrupts, 17-19
monitor channel, 17-14
operation, 17-5
overview, 1-8
PCM highway conversion with ISDN, 12-5
receiving data, 17-7
registers, 17-5
signal conversion, 17-14
signal descriptions, 3-27
signals, 17-13
software considerations, 17-20
structure, 17-8
TIC bus, 17-16
transmitting data, 17-6
upstream monitor channel transmission, 17-15
upstream TIC format, 17-16
usage, 17-5
with TSA, 16-14
GCI_DCL_A signal, 3-27
GCI_DD_A signal, 3-27
GCI_DU_A signal, 3-27
GCI_FSC_A signal, 3-27
GCIRD0 register, 17-5
GCIRD0P register, 17-5
GCIRD1 register, 17-5
GCIRD1P register, 17-5
GCITD0 register, 17-5
GCITD1 register, 17-5
GDxCON0 register, 8-4, 8-5
GDxCON1 register, 8-4, 8-5
GDxDSTH register, 8-5
GDxDSTL register, 8-4, 8-5
GDxSRCH register, 8-4, 8-5
GDxSRCL register, 8-4, 8-5
GDxTC register, 8-5
general circuit interface. See GCI.
general-purpose DMA
See also DMA, general-purpose.
definition, Glossary-4
GICRD register, 17-5
GICRDP register, 17-5
GICTD register, 17-5
GIMSK register, 17-5
GISTAT register, 17-5
GMRD register, 17-5
GMRDP register, 17-5
GMTD register, 17-5
GPCON register, 17-5
ground pins, 3-16
GTIC register, 17-5
Index
Am186™CC/CH/CU Microcontrollers User's Manual
half duplex
definition, Glossary-4
description, 12-8
handling USB data, 18-18
hardware considerations
chip select, 5-10
DRAM, 6-6
emulator support, 4-5
HDLC, 15-20
programmable I/O (PIO), 9-7
system, 3-34
UART, 13-22
watchdog timer, 11-4
hardware flow control
DMA, 8-24
overview, 12-6
UART, 13-13
hardware interrupt, definition, Glossary-4
HDLC
block diagram, 15-2
comparison to other devices, 15-21
control application, 12-4
CTS control, 15-14
definition, Glossary-4
frame, 15-1
general options, 15-9
hardware considerations, 15-20
initialization, 15-21
interface, 15-7
interrupts, 15-20
operation, 15-7
overview, 1-7
programmed I/O, 15-8
receive interrupt, 15-20
receiver, 15-14, 15-19
receiver block diagram, 15-15
register summary, 15-6
RTR timing, 15-18
signal descriptions, 3-23
software considerations, 15-21
transmit interrupt, 15-20
transmitter, 15-10, 15-18
transmitter block diagram, 15-10
usage, 15-7
with SmartDMA channel, 15-18
High-Speed UART. See UART.
HLDA signal, 3-12
HOLD latency, definition, Glossary-4
HOLD signal, 3-13
host, definition, Glossary-4
HSPAB0 register, 13-4
HSPAB1 register, 13-4
HSPAB2 register, 13-4
H
Index-7